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<title>u-boot.git/drivers, branch v2025.07-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/drivers?h=v2025.07-rc3</id>
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<updated>2025-05-25T13:44:13Z</updated>
<entry>
<title>usb: ulpi: Clean up how we enable support</title>
<updated>2025-05-25T13:44:13Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-03-15T01:27:36Z</published>
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<id>urn:sha1:831a38483cf21b395bb0d9d7a34fb9b430e9bb86</id>
<content type='text'>
The way we enable ULPI support today isn't something that should work.
The "optional" keyword in a choice statement is not a documented
feature. To make this work in a supported way, make USB_ULPI something
we ask about if USB_HOST is set. Next, we move the choice of what
viewer to use to be after the framework portion and to depend on that.
We then borrow a few words from the top-level README to make the help
text here clearer. Finally we make the Qualcomm driver select ULPI as
it's required and we make the tegra driver not duplicate a check that
Kconfig now handles for us.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>usb: ulpi: Remove unused omap-ulpi-viewport driver</title>
<updated>2025-05-25T13:44:13Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-03-15T01:27:35Z</published>
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<id>urn:sha1:cd9c8814b0cd0200b68f96406b3ce9f2b1a6af87</id>
<content type='text'>
The last platform to enable this driver was removed in 2019. Remove this
unused code and documentation now.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>usb: dwc3: core: Fix timeout check</title>
<updated>2025-05-25T13:44:13Z</updated>
<author>
<name>Varadarajan Narayanan</name>
<email>quic_varada@quicinc.com</email>
</author>
<published>2025-01-15T06:20:44Z</published>
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<id>urn:sha1:068f83499c2f8299c6172c511ec875eef2b26a6f</id>
<content type='text'>
dwc3_core_init loops 'timeout' times to check if the IP block is out
of reset using 'while (timeout--)'. If there is some issue and
the block doesn't come out of reset, the loop will run till
'timeout' becomes zero and the post decrement operator would set
timeout to 0xffffffff. Though the IP block is not out reset, the
subsequent if check 'if !timeout' would fail as timeout is not
equal to zero and the function proceeds with the initialization.

Use poll API instead to resolve this.

Signed-off-by: Varadarajan Narayanan &lt;quic_varada@quicinc.com&gt;
Reviewed-by: Mattijs Korpershoek &lt;mkorpershoek@baylibre.com&gt;
Reviewed-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-imx-master-20250522' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx</title>
<updated>2025-05-22T14:41:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-05-22T14:41:25Z</published>
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<id>urn:sha1:df5dcf7b7eb66f74262c5e501f813aac759557f2</id>
<content type='text'>
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/26275

- Fix boot regression on imx8mn_bsh_smm_s2/s2pro.
- Fix reset on imx6ulz_smm_m2.
- Adjust DDR initialization on imx6ulz_smm_m2.
- Fix CAAM startup error.
</content>
</entry>
<entry>
<title>caam: Fix CAAM error on startup</title>
<updated>2025-05-22T12:01:51Z</updated>
<author>
<name>Olaf Baehring</name>
<email>olaf.baehring@draeger.com</email>
</author>
<published>2025-05-21T11:03:40Z</published>
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<id>urn:sha1:159b6f0e119962ce5da645f548cefe9196c8778e</id>
<content type='text'>
In rare cases U-Boot returns an error message when intantiating the RNG
of the CAAM device:
“SEC0:  RNG4 SH0 instantiation failed with error 0xffffffff”
This  means, that even when the CAAM device reports a finished
descriptor, none is found in the output ring.
This might be caused by a missing cache invalidation before
reading the memory of the output ring
This patch moves the cache invalidation of the output ring from start of
the job to immediately after the notification from hardware where the
output ring will be read.

Signed-off-by: Olaf Baehring &lt;olaf.baehring@draeger.com&gt;
Signed-off-by: Fabio Estevam &lt;festevam@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: thead: Port clock controller driver of TH1520 SoC</title>
<updated>2025-05-21T08:49:57Z</updated>
<author>
<name>Yao Zi</name>
<email>ziyao@disroot.org</email>
</author>
<published>2025-05-16T03:05:23Z</published>
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<id>urn:sha1:e6bfa6fc94f655545f4c79b9a9939cfeb97a3a89</id>
<content type='text'>
The driver is adapted from Linux kernel's version of clk-th1520-ap.c,
with only output clocks for external sensors, which are barely useful in
bootloaders, removed.

Same as the mainline driver, it currently lacks of ability to enable and
reconfigure PLLs, which could be implemented later.

Signed-off-by: Yao Zi &lt;ziyao@disroot.org&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>ram: thead: Add initial DDR controller support for TH1520</title>
<updated>2025-05-21T08:49:52Z</updated>
<author>
<name>Yao Zi</name>
<email>ziyao@disroot.org</email>
</author>
<published>2025-05-13T09:04:57Z</published>
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<id>urn:sha1:05240d541a407fbb62eec43f40a2b831bb1c1fe0</id>
<content type='text'>
This patch cleans the vendor code of DDR initialization up, converts the
driver to fit in DM framework and use a firmware[1] packaged by binman to
ship PHY configuration.

Currently the driver is only capable of initializing the controller to
work with dual-rank 3733MHz LPDDR4, which is shipped by 16GiB variants
of LicheePi 4A boards and I could test with. Support for other
configurations could be easily added later.

Link: https://github.com/ziyao233/th1520-firmware # [1]
Signed-off-by: Yao Zi &lt;ziyao@disroot.org&gt;
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
</entry>
<entry>
<title>mmc: cv1800b: Fix build without MMC_SUPPORTS_TUNING</title>
<updated>2025-05-20T15:11:52Z</updated>
<author>
<name>Alexander Sverdlin</name>
<email>alexander.sverdlin@gmail.com</email>
</author>
<published>2025-04-27T21:46:19Z</published>
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<id>urn:sha1:72ba30aeccfc225152c19991732228f95b050ca4</id>
<content type='text'>
That's how it looks like without CONFIG_MMC_SUPPORTS_TUNING before the
patch:

aarch64-buildroot-linux-gnu-ld.bfd: drivers/mmc/cv1800b_sdhci.o: in function `cv1800b_execute_tuning':
drivers/mmc/cv1800b_sdhci.c:47:(.text.cv1800b_execute_tuning+0x50): undefined reference to `mmc_send_tuning'

Signed-off-by: Alexander Sverdlin &lt;alexander.sverdlin@gmail.com&gt;
Reviewed-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
</content>
</entry>
<entry>
<title>net: fsl_enetc: fix imdio register calculation</title>
<updated>2025-05-12T21:43:19Z</updated>
<author>
<name>Thomas Schaefer</name>
<email>thomas.schaefer@kontron.com</email>
</author>
<published>2025-04-28T09:59:46Z</published>
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<id>urn:sha1:9373e5aecfc5baf94534e2e7cc2270a09fc349b4</id>
<content type='text'>
With commit cc4e8af2c552, fsl_enetc register accessors have been split to
handle different register offsets on different SoCs. However, for
internal MDIO register calculation, only ENETC_PM_IMDIO_BASE was fixed
without adding the SoC specific MAC register offset.

As a result, the network support for the Kontron SMARC-sAL28 and
probably other boards based on the LS1028A CPU is broken.

Add the SoC specific MAC register offset to calculation of imdio.priv to
fix this.

Fixes: cc4e8af2c552 ("net: fsl_enetc: Split register accessors")
Signed-off-by: Thomas Schaefer &lt;thomas.schaefer@kontron.com&gt;
Signed-off-by: Heiko Thiery &lt;heiko.thiery@gmail.com&gt;
Reviewed-by: Michael Walle &lt;mwalle@kernel.org&gt;
Reviewed-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt;
Tested-by: Vladimir Oltean &lt;vladimir.oltean@nxp.com&gt; # LS1028A
Tested-by: Tim Harvey &lt;tharvey@gateworks.com&gt; # imx95_19x19_evk
Reviewed-by: Marek Vasut &lt;marex@denx.de&gt;
Reviewed-by: Alice Guo &lt;alice.guo@nxp.com&gt;
</content>
</entry>
<entry>
<title>spi: fspi: dev_dbg() call assumes fdt_addr_t always a long long</title>
<updated>2025-05-12T21:42:53Z</updated>
<author>
<name>Jonathan Currier</name>
<email>dullfire@yahoo.com</email>
</author>
<published>2025-05-07T08:36:23Z</published>
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<id>urn:sha1:e2ebfe3c9a1b66ab7c9c86449ceb4a11986afb46</id>
<content type='text'>
On 32-bit systems, e.g. i.mxrt-1170 fdt_addr_t may only be 32-bit.
Cast to a "long long" for garbage avoidance.

Signed-off-by: Jonathan Currier &lt;dullfire@yahoo.com&gt;
</content>
</entry>
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