These files had '#include<file.h>' rather than '#include <file.h>' which
while functional is not the correct style.

Signed-off-by: Tom Rini <trini@konsulko.com>

Add "in SPL" to the SPL related driver help texts.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

Use regulator_set_enable_if_allowed() to avoid failure if regulator is
shared between multiple devices.

Signed-off-by: Ben Wolsieffer <ben.wolsieffer@hefring.com>

Replace MII with RMII as it is a Reduced Media-Independent Interface.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>

If reset property is missing in DT, then we get this warning:
	designware_i2c@0: Can't get reset: -2

Avoid this by checking if reset DT property is present, first.

Fixes: 622597dee4f ("i2c: designware: add reset ctrl to driver")
Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
Reviewed-by: Heiko Schocher <hs@nabladev.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>

Initialize mtd->writesize in nand_init() as otherwise
nand_page_size() returns 0 and this affects NAND read
operations.

Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 585
Figure 9.3.2 Software Reset flow (B) indicates that for peripherals in HSC
domain, after reset has been asserted by writing a matching reset bit into
register SRCR, it is mandatory to wait 1ms.

Because it is the controller driver which can determine whether or not the
controller is in HSC domain based on its compatible string, add the missing
delay into the controller driver.

This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear
whether S4 is affected as well. This patch does apply the extra delay on
R-Car S4 as well.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Assure the reset is latched and the core is ready for DBI access.
On R-Car V4H, the PCIe reset is asynchronized and does not take
effect immediately, but needs a short time to complete. In case
DBI access happens in that short time, that access generates an
SError. Make sure that condition can never happen, read back the
state of the reset which should turn the asynchronized reset into
synchronized one, and wait a little over 1ms to add additional
safety margin.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr. 21, 2025 page 4581
Figure 104.3b Initial Setting of PCIEC(example), third quarter of the figure
indicates that register 0xf8 should be polled until bit 18 becomes set to 1.

Register 0xf8 bit 18 is 0 immediately after write to PCIERSTCTRL1 and is set
to 1 in less than 1 ms afterward. The current readl_poll_timeout() break
condition is inverted and returns when register 0xf8 bit 18 is set to 0,
which in most cases means immediately. In case CONFIG_DEBUG_LOCK_ALLOC=y ,
the timing changes just enough for the first readl_poll_timeout() poll to
already read register 0xf8 bit 18 as 1 and afterward never read register
0xf8 bit 18 as 0, which leads to timeout and failure to start the PCIe
controller.

Fix this by inverting the poll condition to match the reference manual
initialization sequence.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

MUX_MMIO is needed by HBMC in SPL stage. Enable it at SPL as well
as u-boot proper stage.

Signed-off-by: Anurag Dutta <a-dutta@ti.com>
Reviewed-by: Udit Kumar <u-kumar1@ti.com>