Support for using "u-boot,dm-..." rather than "bootph-..." has been deprecated since February 2023. Any platforms using this have had a console message saying to migrate by 2023.07. Go and remove all support here now, for the v2026.01 release. The results of this change that aren't clear from the above are that we still have a checkpatch.pl error message, and document in doc/develop/spl.rst that they have been migrated since 2023. We also change the key2dtsi.py tool to use the correct bootph phase rather than the legacy phase. Signed-off-by: Tom Rini <trini@konsulko.com>
Remaining R-Car Gen5 driver patches, MMC, clock. Also a trivial adjustment for mailbox core to allow operation without .recv callback.
Hrushikesh Salunke <h-salunke@ti.com> says: This series enables PCIe Endpoint mode on TI's J784S4 SoC. The J784S4 SoC features two Cadence PCIe controller instances (PCIe0 and PCIe1) that can operate in endpoint mode. This series adds support for configuring these controllers with up to 4 lanes. Key changes include: - Adding a stabilization delay after power domain reset to prevent timing-related initialization issues - SERDES mux configuration support for proper lane routing, which is essential for SoCs where SERDES lanes are shared between multiple controllers (PCIe, USB, etc.) with different configurations across boot phases - J784S4 SoC endpoint configuration with 4-lane support - Disabling unconfigured endpoint functions to prevent enumeration issues on the Root Complex side This series has been tested on J784S4 EVM with PCIe endpoint boot configuration. Following are the corresponding test logs. https://gist.github.com/hrushikesh221/331d65f45f43fd138f57e6adb61c4332 Link: https://lore.kernel.org/r/20251023114604.3655625-1-h-salunke@ti.com
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> says:
This patch series adds basic support for the boards based on Airoha
EN7523/EN7529/EN7562 SoCs. Due to ATF restrictions these boards are
able to run 32-bit OS only.
This patch series adds support for the following hardware:
* console UART
* ethernet controller/switch
* spinand flash (in non-dma mode)
The following issues may be expected:
* Extra slow UBI attaching in U-Boot (up to 20 sec with fastmap enabled).
This is caused by the lack of DMA support in the U-Boot airoha-snfi driver.
* Linux airoha-snfi driver in some cases might damage you flash data
(see: https://lore.kernel.org/lkml/20251012121707.2296160-15-mikhail.kshevetskiy@iopsys.eu/)
* Latest linux kernel is recommended to properly support flashes
with more than one plane per lun
(see: https://lore.kernel.org/lkml/20251012121707.2296160-7-mikhail.kshevetskiy@iopsys.eu/)
* It's NOT recommended to use flashes working in continuous mode because
U-Boot airoha-snfi driver does not support such flashes properly.
The patches was tested on the board:
- SoC: Airoha EN7562
- RAM: 512 MB
- SPI NAND: 4 Gbit, made by Toshiba
- Linux boot: was NOT tested
The U-Boot was chain-loaded from the running U-Boot. Airoha ATF-2.3 does
not allow easily chain-loading of U-Boot from U-Boot, so a special FIT
image (mimic linux kernel) was created
1) Create u-boot.its file with the following contents:
=== cut here ===
/dts-v1/;
/ {
description = "ARM OpenWrt FIT (Flattened Image Tree)";
#address-cells = <1>;
images {
u-boot-ram {
description = "OpenWrt U-Boot RAM image";
data = /incbin/("u-boot.bin.lzma");
type = "kernel";
arch = "arm";
os = "linux";
compression = "lzma";
load = <0x81e00000>;
entry = <0x81e00000>;
hash@1 {
algo = "crc32";
};
hash@2 {
algo = "sha1";
};
};
fdt-1 {
description = "OpenWrt device tree blob";
data = /incbin/("dts/upstream/src/arm/airoha/en7523-evb.dtb");
type = "flat_dt";
arch = "arm";
compression = "none";
hash@1 {
algo = "crc32";
};
hash@2 {
algo = "sha1";
};
};
};
configurations {
default = "config-ram-uboot";
config-ram-uboot {
description = "OpenWrt RAM U-Boot";
kernel = "u-boot-ram";
fdt = "fdt-1";
};
};
};
==================
2) Create u-boot.itb image to chain-load new u-boot from the old one
lzma_alone e u-boot.bin u-boot.bin.lzma
mkimage -f u-boot.its u-boot.itb
3) Load new u-boot from the old one
U-Boot> tftpboot u-boot.itb && bootm
Link: https://lore.kernel.org/r/20251101004503.2379529-1-mikhail.kshevetskiy@iopsys.eu
TI's J784S4 SoC has two instances of PCIe Controller namely PCIe0 and PCIe1 which are Cadence PCIe Controllers. Add support to configure PCIe instances in Endpoint mode of operation. While at it disable all endpoint functions except function 0 during probe to prevent the Root Complex from enumerating unconfigured functions. This ensures only properly configured endpoint functions are visible to the host and avoids enumeration issues with multi-function devices. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Probe the mux device early in the SERDES configuration flow to ensure proper lane routing before PHY initialization. This is required for SoCs where SERDES lanes can be muxed between different controllers (PCIe, USB, etc), and different mux configurations are required between different boot phases. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Add a 1ms delay after powering on the PCIe power domain to ensure the controller stabilizes before subsequent operations. This prevents potential timing issues during PCIe endpoint initialization. The delay allows sufficient time for the power domain to fully come up and the hardware to be in a stable state before configuration begins. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com>
Add support for Ethernet controller present in Airoha en7523/en7529/en7562. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
This allow us remove some an7581/an7583 specific code and use a common code instead. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
This adds reset controller support for airoha en7523/en7529/en7562 SoCs. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>