u-boot.git/include/asm-arm/arch-davinci, branch v2009.11 Unnamed repository; edit this file 'description' to name the repository. Coding Style cleanup; update CHANGELOG, prepare -rc1 2009-10-27T23:49:47+00:00 Wolfgang Denk wd@denx.de 2009-10-27T23:49:47+00:00 4946775c6db52dba28f72ba3525764b54f1d4593 Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
TI DaVinci: Fix DM6467 EVM Compilation Warning 2009-10-24T14:55:24+00:00 Sandeep Paulraj s-paulraj@ti.com 2009-10-13T16:32:32+00:00 11b0102218bbb50ac5c04f1521f2a22ed4e90cf1 Due to new TI boards being added to U-Boot, the hardware.h is getting very messy. The warning being fixed is due to the EMIF addresses being redefined. The long term solution(after 2009.11) to this is to have SOC specific header files. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 
Due to new TI boards being added to U-Boot, the hardware.h
is getting very messy. The warning being fixed is due to
the EMIF addresses being redefined.

The long term solution(after 2009.11) to this is to
have SOC specific header files.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
TI: DaVinci: GPIO header file and definitions 2009-10-13T11:17:37+00:00 Sandeep Paulraj s-paulraj@ti.com 2009-09-29T14:02:38+00:00 00e1665a3cf956e09ac2ce86ef6ec459f6bfb33c Some DaVinci SOC's use GPIOs to enable EMAC and DM9000. This patch adds some definitions for GPIO registers and also adds structures for GPIO. A separate header file is being added so that in future we can have a DaVinci GPIO driver similer to OMAP. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com> 
Some DaVinci SOC's use GPIOs to enable EMAC and DM9000.
This patch adds some definitions for GPIO registers and also adds
structures for GPIO.
A separate header file is being added so that in future we
can have a DaVinci GPIO driver similer to OMAP.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
TI: DaVinci DM646x: Update flag used to represent DM646x SOC's 2009-10-13T11:17:37+00:00 Sandeep Paulraj s-paulraj@ti.com 2009-09-18T21:30:05+00:00 95ae803afbdd9f673c94b992ea624a10d252afc2 In the DaVinci specific code, we use both CONFIG_SOC_DM646X and CONFIG_SOC_DM646x to represent DM646x specific code. This patch changes occurrences of CONFIG_SOC_DM646x to CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use the flag CONFIG_SOC_DM644X. We want some uniformity. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Acked-by: Tom Rix <Tom.Rix@windriver.com> 
In the DaVinci specific code, we use both CONFIG_SOC_DM646X and
CONFIG_SOC_DM646x to represent DM646x specific code.
This patch changes occurrences of CONFIG_SOC_DM646x to
CONFIG_SOC_DM646X. This is because for DM644x series of SOCs we use
the flag CONFIG_SOC_DM644X. We want some uniformity.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
TI DaVinci: DM646x: Initial Support for DM646x SOC 2009-10-13T11:17:34+00:00 Sandeep Paulraj s-paulraj@ti.com 2009-09-08T15:37:39+00:00 7908c97a106765ad8816bf2271a5bf315728b274 DM646x is an SOC from TI which has both an ARM and a DSP. There are multiple variants of the SOC mainly dealing with different core speeds. This patch adds the initial framework for the DM646x SOC. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> 
DM646x is an SOC from TI which has both an ARM and a DSP.
There are multiple variants of the SOC mainly dealing with different
core speeds.
This patch adds the initial framework for the DM646x SOC.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
NAND: DaVinci: V2 Adding 4 BIT ECC support 2009-08-26T20:37:03+00:00 Sandeep Paulraj s-paulraj@ti.com 2009-08-18T14:10:42+00:00 77b351cd0f20483eefa09bebebb3e0cbf5555b2c This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com> 
This patch adds 4 BIT ECC support in the DaVinci NAND
driver. Tested on both the DM355 and DM365.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
davinci_nand chipselect/init cleanup 2009-07-07T22:58:03+00:00 David Brownell dbrownell@users.sourceforge.net 2009-05-10T22:43:01+00:00 154b5484ac7dcbcd0fb5ba388d930b02f87fa302 Update chipselect handling in davinci_nand.c so that it can handle 2 GByte chips the same way Linux does: as one device, even though it has two halves with independent chip selects. For such chips the "nand info" command reports: Device 0: 2x nand0, sector size 128 KiB Switch to use the default chipselect function unless the board really needs its own. The logic for the Sonata board moves out of the driver into board-specific code. (Which doesn't affect current build breakage if its NAND support is enabled...) Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com> 
Update chipselect handling in davinci_nand.c so that it can
handle 2 GByte chips the same way Linux does:  as one device,
even though it has two halves with independent chip selects.
For such chips the "nand info" command reports:

  Device 0: 2x nand0, sector size 128 KiB

Switch to use the default chipselect function unless the board
really needs its own.  The logic for the Sonata board moves out
of the driver into board-specific code.  (Which doesn't affect
current build breakage if its NAND support is enabled...)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>
NAND DaVinci: Update to ALE/CLE Mask values 2009-07-07T22:58:02+00:00 Sandeep Paulraj s-paulraj@ti.com 2009-05-09T16:35:20+00:00 496863b2440dd7cd69a1ad2443a9badd5f8968d1 All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8 except the DM646x. This was decided by the design team driving the design. This patch updates the CLE and ALE values for DM646x. Updated patches for DM646x will be sent shortly. This applies to u-boot-nand-flash git Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com> 
All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8
except the DM646x. This was decided by the design team driving the design.
This patch updates the CLE and ALE values for DM646x.
Updated patches for DM646x will be sent shortly.
This applies to u-boot-nand-flash git

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
ARM DaVinci: Changing ALE Mask Value 2009-07-07T22:58:02+00:00 Sandeep Paulraj s-paulraj@ti.com 2009-04-29T13:47:09+00:00 0c1684437ef810c503df29e8d73f63191aa63862 The ALE mask used by DaVinci SOCs is wrong. The patch changes the mask value from '0xa' to '0x8'. This is the mask we use for all TI releases. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com> 
The ALE mask used by DaVinci SOCs is wrong. The patch changes the mask value
from '0xa' to '0x8'. This is the mask we use for all TI releases.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
davinci_nand: cleanup II (CONFIG_SYS_DAVINCI_BROKEN_ECC) 2009-07-07T22:58:01+00:00 David Brownell dbrownell@users.sourceforge.net 2009-04-28T20:19:53+00:00 6e29ed8e576a6900c5d8dcde36b423ac576894dc Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option. It's not just nasty; it's also unused by any current boards, and doesn't even match the main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC on newer chips that support it). DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30, match non-BROKEN code paths for 1-bit HW ECC. The BROKEN code paths do seem to partially match what MontaVista/TI kernels (4.0/2.6.10, and 5.0/2.6.18) do ... but only for small pages. Large page support is really broken (and it's unclear just what software it was trying to match!), and the ECC layout was making three more bytes available for use by filesystem (or whatever) code. Since this option itself seems broken, remove it. Add a comment about the MV/TI compat issue, and the most straightforward way to address it (should someone really need to solve it). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Scott Wood <scottwood@freescale.com> 
Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option.  It's not just nasty;
it's also unused by any current boards, and doesn't even match the
main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC
on newer chips that support it).

DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30,
match non-BROKEN code paths for 1-bit HW ECC.  The BROKEN code paths
do seem to partially match what MontaVista/TI kernels (4.0/2.6.10,
and 5.0/2.6.18) do ... but only for small pages.  Large page support
is really broken (and it's unclear just what software it was trying
to match!), and the ECC layout was making three more bytes available
for use by filesystem (or whatever) code.

Since this option itself seems broken, remove it.  Add a comment
about the MV/TI compat issue, and the most straightforward way to
address it (should someone really need to solve it).

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Scott Wood <scottwood@freescale.com>