u-boot.git/include/asm-arm/arch-omap3, branch main

Move architecture-specific includes to arch/$ARCH/include/asm

2010-04-13T07:13:12Z

This helps to clean up the include/ directory so that it only contains non-architecture-specific headers and also matches Linux's directory layout which many U-Boot developers are already familiar with. Signed-off-by: Peter Tyser

OMAP3 Move declaration of gpmc_cfg.

2010-02-12T18:31:53Z

Every omap3 board config file declared the global variable gpmc_cfg. This changes moves the declaration to a better location in the arch dependent header file cpu.h. Signed-off-by: Tom Rix Signed-off-by: Sandeep Paulraj

OMAP3: Fix SDRC init

2009-11-27T22:26:17Z

Defaults are for Infineon DDR timings. Since none of the supported boards currently do XIP boot, these seem to be faulty. fix the values as per the calculations(ACTIMA,B), conf the sdrc power with pwdnen and wakeupproc bits Signed-off-by: Nishanth Menon

OMAP3:SDRC: introduce DDR types

2009-11-27T22:26:16Z

Micron DDR timings based on: http://www.sakoman.net/cgi-bin/gitweb.cgi?p=x-load-omap3.git;a=blob;f=include/asm/arch-omap3/mem.h;h=e6fbfe3947f5d0d85fea776e30821d4017316d86;hb=HEAD Introduce Micron DDR timings and provide CONFIG_OMAP3_INFINEON_DDR and CONFIG_OMAP3_MICRON_DDR config options to allow for platform files to setup their timings as per the type of DDR selected Reported-by: Steve Sakoman in http://www.nabble.com/forum/Permalink.jtp?root=25779518&post=25959734&page=y Signed-off-by: Nishanth Menon

OMAP3:SDRC: Cleanup references to SDP

2009-11-27T22:26:16Z

Remove SDP referenced unused defines Signed-off-by: Nishanth Menon

OMAP2/3: I2C: Add support for second and third bus

2009-11-16T06:25:15Z

Add support to use second and third I2C bus, too. Bus 0 is still the default, but by calling i2c_set_bus_num(1/2) before doing I2C accesses, code can switch to bus 1 and 2, too. Don't forget to switch back afterwards, then. Signed-off-by: Dirk Behme

TI OMAP3: make gpmc_config as const

2009-10-24T14:55:24Z

gpmc_config should not be a variant as it is board specific hence make it a const parameter Fixes issues identified by Dirk: - build issue for zoom2 - warnings for all other OMAP3 platforms using nand/onenand etc Signed-off-by: Nishanth Menon

OMAP3: export enable_gpmc_cs_config to board files

2009-10-18T21:52:53Z

Export enable_gpmc_cs_config into common header to prevent warning: warning: implicit declaration of function 'enable_gpmc_cs_config' Signed-off-by: Nishanth Menon

OMAP3 MMC: Fix warning dereferencing type-punned pointer

2009-10-13T11:17:36Z

Fix warning Dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Dirk Behme CC: Steve Sakoman Acked-by: Tom Rix

OMAP3 Move cache routine to cache.S

2009-10-13T11:17:33Z

v7_flush_dcache_all, because it depends on omap ROM code is not generic. Rename the function to 'invalidate_dcache' and move it to the omap cpu directory. Collect the other omap cache routines l2_cache_enable and l2_cache_disable with invalide_dcache into cache.S. This means removing the old cache.c file that contained l2_cache_enable and l2_cache_disable. The conversion from cache.c to cache.S was done most through disassembling the uboot binary. The only significant change was to change the comparision for the return of get_cpu_rev from cmp r0, #0 beq earlier_than_label Which was lost information to cmp r0, #CPU_3XX_ES20 blt earlier_than_label The paths through the enable routine were verified by adding an infinite loop and seeing the hang. Then removing the infinite loop and seeing it continue. The disable routine is similar enough that it was not tested with this method. Run tested by cold booting from nand on beagle and zoom1. Compile tested on MAKEALL arm. Signed-off-by: Tom Rix