u-boot.git/include/asm-ppc/config.h, branch v2009.11 Unnamed repository; edit this file 'description' to name the repository. 85xx: MP Boot Page Translation update 2009-10-27T14:34:57+00:00 Peter Tyser ptyser@xes-inc.com 2009-10-23T20:55:47+00:00 5ccd29c3679b3669b0bde5c501c1aa0f325a7acb This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
This change has 3 goals:
- Have secondary cores be released into spin loops at their 'true'
  address in SDRAM.  Previously, secondary cores were put into spin
  loops in the 0xfffffxxx address range which required that boot page
  translation was always enabled while cores were in their spin loops.

- Allow the TLB window that the primary core uses to access the
  secondary cores boot page to be placed at any address.  Previously, a
  TLB window at 0xfffff000 was always used to access the seconary cores'
  boot page.  This TLB address requirement overlapped with other
  peripherals on some boards (eg XPedite5370).  By default, the boot
  page TLB will still use the 0xfffffxxx address range, but this can be
  overridden on a board-by-board basis by defining a custom
  CONFIG_BPTR_VIRT_ADDR.  Note that the TLB used to map the boot page
  remains in use while U-Boot executes.  Previously it was only
  temporarily used, then restored to its initial value.

- Allow Boot Page Translation to be disabled on bootup.  Previously,
  Boot Page Translation was always left enabled after secondary cores
  were brought out of reset.  This caused the 0xfffffxxx address range
  to somewhat "magically" be translated to an address in SDRAM.  Some
  boards may not want this oddity in their memory map, so defining
  CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after
  the secondary cores are initialized.

These changes are only applicable to 85xx boards with CONFIG_MP defined.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ppc: Enable full relocation to RAM 2009-10-03T08:15:45+00:00 Peter Tyser ptyser@xes-inc.com 2009-09-21T16:20:25+00:00 858290178f222d998b6425d85cf06822467918f3 The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> 
The following changes allow U-Boot to fully relocate from flash to
RAM:
 - Remove linker scripts' .fixup sections from the .text section
 - Add -mrelocatable to PLATFORM_RELFLAGS for all boards
 - Define CONFIG_RELOC_FIXUP_WORKS for all boards

Previously, U-Boot would partially relocate, but statically initialized
pointers needed to be manually relocated.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
ppc/p4080: Add various p4080 related defines (and p4040) 2009-09-24T17:05:28+00:00 Kumar Gala galak@kernel.crashing.org 2009-03-19T07:39:17+00:00 7e4259bba4c56536760e42d32dacfb3233f216fd There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
85xx: Added CONFIG_MAX_CPUS for P1020 2009-08-28T22:12:41+00:00 Poonam Aggrwal poonam.aggrwal@freescale.com 2009-08-20T13:25:35+00:00 3b1f243b8dad30a646a0f056b0268519eadbc3c5 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx 2009-08-28T22:12:38+00:00 Poonam Aggrwal poonam.aggrwal@freescale.com 2009-07-31T06:38:14+00:00 0e870980a64584a591af775bb9c9fe9450124df9 The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ppc: Fix compile error for boards with CONFIG_DDR_ECC 2009-07-17T21:44:42+00:00 Peter Tyser ptyser@xes-inc.com 2009-07-15T05:01:08+00:00 f732a7598fa36d48241df20b1a1f4cdbf09f75ee A bug was introduced by commit e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae which affected non-MPC83xx/85xx/86xx ppc boards which had CONFIG_DDR_ECC defined and resulted in errors such as: Configuring for canyonlands board... fsl_dma.c:50:2: error: #error "Freescale DMA engine not supported on your processor" make[1]: *** No rule to make target `.depend', needed by `libdma.a'. Stop. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> 
A bug was introduced by commit e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae
which affected non-MPC83xx/85xx/86xx ppc boards which had CONFIG_DDR_ECC
defined and resulted in errors such as:

Configuring for canyonlands board...
fsl_dma.c:50:2: error: #error "Freescale DMA engine not supported on your
processor"
make[1]: *** No rule to make target `.depend', needed by `libdma.a'.  Stop.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
83xx: Add support for fsl_dma driver 2009-07-02T16:15:57+00:00 Peter Tyser ptyser@xes-inc.com 2009-06-30T22:15:51+00:00 e94e460c6e8741f42dab6d8dd4b596ba5d9d79ae Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Reviewed-by: Ira W. Snyder <iws@ovro.caltech.edu> Tested-by: Ira W. Snyder <iws@ovro.caltech.edu> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Reviewed-by: Ira W. Snyder <iws@ovro.caltech.edu>
Tested-by: Ira W. Snyder <iws@ovro.caltech.edu>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
8xxx: Break out DMA code to a common file 2009-07-02T04:01:51+00:00 Peter Tyser ptyser@xes-inc.com 2009-06-30T22:15:40+00:00 017f11f68ef543e866be033bcb7b8058a8a380d8 DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the
previous CONFIG_DDR_ECC

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
MPC86xx: set CONFIG_MAX_MEM_MAPPED to 2G by default 2009-02-23T21:50:05+00:00 Becky Bruce beckyb@kernel.crashing.org 2009-02-23T19:56:51+00:00 bd76729bcbfd64b5d016a9b936f058931fc06eaf Currently, we get 256MB as the default, but since all the 86xx board configs define a 2G BAT mapping for RAM, raise default to 2G. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com> 
Currently, we get 256MB as the default, but since all the 86xx
board configs define a 2G BAT mapping for RAM, raise default
to 2G.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Jon Loeliger <jdl@freescale.com>
85xx: Fix how we map DDR memory 2009-02-17T00:05:51+00:00 Kumar Gala galak@kernel.crashing.org 2009-02-06T15:56:35+00:00 f8523cb0815b2d3d2d780b7d49ca614105555f58 Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Previously we only allowed power-of-two memory sizes and didnt
handle >2G of memory.  Now we will map up to CONFIG_MAX_MEM_MAPPED
and should properly handle any size that we can make in the TLBs
we have available to us

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>