u-boot.git/include/asm-ppc/processor.h, branch next

Move architecture-specific includes to arch/$ARCH/include/asm

2010-04-13T07:13:12+00:00

This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.

Signed-off-by: Peter Tyser

85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater

2010-04-07T05:21:27+00:00

The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize
the performance of mbar/eieio instructions.

Signed-off-by: Sandeep Gopalpet

85xx: Added various P1012/P1013/P1021/P1022 defines

2010-04-07T05:21:22+00:00

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config

Signed-off-by: Haiying Wang 
Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Kumar Gala

85xx: Add defines for BUCSR bits to make code more readable

2010-04-07T05:08:17+00:00

Signed-off-by: Kumar Gala

85xx: Fix enabling of L1 cache parity on secondary cores

2010-03-30T15:48:30+00:00

Use the same code between primary and secondary cores to init the
L1 cache.  We were not enabling cache parity on the secondary cores.

Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks.  Than enables the cache and
makes sure its enabled before continuing.

Signed-off-by: Kumar Gala

ppc: Added macro to test for specific SVR revision

2010-01-05T19:49:09+00:00

Various SoC errata are specific to a given revision of silicon. This
patch gives us a simple macro to use when doing such tests.

Signed-off-by: Kumar Gala

ppc4xx: Add PPC405EX(r) Rev D support

2009-10-07T07:14:27+00:00

Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:

0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec

Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.

Signed-off-by: Stefan Roese 
Cc: Phong Vo"

ppc/p4080: Add various p4080 related defines (and p4040)

2009-09-24T17:05:28+00:00

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala

ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.

2009-09-16T02:30:08+00:00

Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood

ppc/85xx,86xx: Handling Unknown SOC version

2009-09-08T14:10:08+00:00

Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala