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<title>u-boot.git/include/asm-ppc/processor.h, branch v1.3.1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>85xx start.S cleanup and exception support</title>
<updated>2007-08-14T06:34:21+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2007-08-14T06:34:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=61a21e980a7b9188424d04f1c265fdc5c21c7e85'/>
<id>61a21e980a7b9188424d04f1c265fdc5c21c7e85</id>
<content type='text'>
From: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
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<pre>
From: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fsl_pci_init cleanup.</title>
<updated>2007-08-10T16:39:37+00:00</updated>
<author>
<name>Ed Swarthout</name>
<email>Ed.Swarthout@freescale.com</email>
</author>
<published>2007-07-27T06:50:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2e4d94f1e3c2961428967a33b6ff2520568391b3'/>
<id>2e4d94f1e3c2961428967a33b6ff2520568391b3</id>
<content type='text'>
Do not enable normal errors created during probe (master abort, perr,
and pcie Invalid Configuration access).

Add CONFIG_PCI_NOSCAN board option to prevent bus scan.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
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<pre>
Do not enable normal errors created during probe (master abort, perr,
and pcie Invalid Configuration access).

Add CONFIG_PCI_NOSCAN board option to prevent bus scan.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Acked-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>cpu/86xx fixes.</title>
<updated>2007-08-10T16:02:32+00:00</updated>
<author>
<name>Jon Loeliger</name>
<email>jdl@freescale.com</email>
</author>
<published>2007-08-02T19:42:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cfc7a7f5bb3273c9951173c788001d45118f141f'/>
<id>cfc7a7f5bb3273c9951173c788001d45118f141f</id>
<content type='text'>
Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Signed-off-by: Jon Loeliger &lt;jdl@freescale.com&gt;
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<pre>
Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Signed-off-by: Jon Loeliger &lt;jdl@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[PPC] Remove unused MSR_USER definition</title>
<updated>2007-07-27T12:22:04+00:00</updated>
<author>
<name>Rafal Jaworowski</name>
<email>raj@semihalf.com</email>
</author>
<published>2007-07-27T12:22:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1863cfb7b100ba0ee3401799457a01dc058745f8'/>
<id>1863cfb7b100ba0ee3401799457a01dc058745f8</id>
<content type='text'>
Signed-off-by: Rafal Jaworowski &lt;raj@semihalf.com&gt;
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<pre>
Signed-off-by: Rafal Jaworowski &lt;raj@semihalf.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Fix breakage of 8xx boards from recent commit.</title>
<updated>2007-07-19T15:12:28+00:00</updated>
<author>
<name>Rafal Jaworowski</name>
<email>raj@semihalf.com</email>
</author>
<published>2007-07-19T15:12:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=cc3023b9f95d7ac959a764471a65001062aecf41'/>
<id>cc3023b9f95d7ac959a764471a65001062aecf41</id>
<content type='text'>
This patch fixes the negative consequences for 8xx of the recent
"ppc4xx: Clean up 440 exceptions handling" commit.

Signed-off-by: Rafal Jaworowski &lt;raj@semihalf.com&gt;
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<pre>
This patch fixes the negative consequences for 8xx of the recent
"ppc4xx: Clean up 440 exceptions handling" commit.

Signed-off-by: Rafal Jaworowski &lt;raj@semihalf.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Coding stylke cleanup; rebuild CHANGELOG</title>
<updated>2007-06-22T21:59:00+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2007-06-22T21:59:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1636d1c8529c006d106287cfbc20cd0a246fe1cb'/>
<id>1636d1c8529c006d106287cfbc20cd0a246fe1cb</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>ppc4xx: Clean up 440 exceptions handling</title>
<updated>2007-06-15T09:19:28+00:00</updated>
<author>
<name>Grzegorz Bernacki</name>
<email>gjb@semihalf.com</email>
</author>
<published>2007-06-15T09:19:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=efa35cf12d914d4caba942acd5a6c45f217de302'/>
<id>efa35cf12d914d4caba942acd5a6c45f217de302</id>
<content type='text'>
- Introduced dedicated switches for building 440 and 405 images required
  for 440-specific machine instructions like 'rfmci' etc.

- Exception vectors moved to the proper location (_start moved away from
  the critical exception handler space, which it occupied)

- CriticalInput now serviced (with default handler)

- MachineCheck properly serviced (added a dedicated handler and return
  subroutine)

- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  unhandled and those not relevant for 4xx were eliminated)

- Eliminated Linux leftovers, removed dead code

Signed-off-by: Grzegorz Bernacki &lt;gjb@semihalf.com&gt;
Signed-off-by: Rafal Jaworowski &lt;raj@semihalf.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
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<pre>
- Introduced dedicated switches for building 440 and 405 images required
  for 440-specific machine instructions like 'rfmci' etc.

- Exception vectors moved to the proper location (_start moved away from
  the critical exception handler space, which it occupied)

- CriticalInput now serviced (with default handler)

- MachineCheck properly serviced (added a dedicated handler and return
  subroutine)

- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  unhandled and those not relevant for 4xx were eliminated)

- Eliminated Linux leftovers, removed dead code

Signed-off-by: Grzegorz Bernacki &lt;gjb@semihalf.com&gt;
Signed-off-by: Rafal Jaworowski &lt;raj@semihalf.com&gt;
Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>[PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message</title>
<updated>2007-05-05T19:35:03+00:00</updated>
<author>
<name>Grzegorz Wianecki</name>
<email>grzegorz.wianecki@gmail.com</email>
</author>
<published>2007-04-29T12:01:54+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a9d87e2707dcb249f6bb7f7ff7e00acd8cda9fd2'/>
<id>a9d87e2707dcb249f6bb7f7ff7e00acd8cda9fd2</id>
<content type='text'>
MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up
message. Use PVR to distinguish between the two variants, and print proper CPU
information.

Signed-off-by: Grzegorz Wianecki &lt;grzegorz.wianecki@gmail.com&gt;
Signed-off-by: Bartlomiej Sieka &lt;tur@semihalf.com&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
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<pre>
MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up
message. Use PVR to distinguish between the two variants, and print proper CPU
information.

Signed-off-by: Grzegorz Wianecki &lt;grzegorz.wianecki@gmail.com&gt;
Signed-off-by: Bartlomiej Sieka &lt;tur@semihalf.com&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Add support for the 8568 MDS board</title>
<updated>2007-05-02T20:50:02+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2007-04-23T07:54:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6743105988fc44d5b0d30388c790607835aae7a6'/>
<id>6743105988fc44d5b0d30388c790607835aae7a6</id>
<content type='text'>
This included some changes to common files:
* Add 8568 processor SVR to various places
* Add support for setting the qe bus-frequency value in the dts
* Add the 8568MDS target to the Makefile

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
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<pre>
This included some changes to common files:
* Add 8568 processor SVR to various places
* Add support for setting the qe bus-frequency value in the dts
* Add the 8568MDS target to the Makefile

Signed-off-by: Andy Fleming &lt;afleming@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Enable 8544 support</title>
<updated>2007-04-24T00:58:28+00:00</updated>
<author>
<name>Andy Fleming</name>
<email>afleming@freescale.com</email>
</author>
<published>2007-04-23T07:24:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=81f481ca708ed6a56bf9c410e3191dbad581c565'/>
<id>81f481ca708ed6a56bf9c410e3191dbad581c565</id>
<content type='text'>
* Add support to the Makefile
* Add 8544 configuration support to the tsec driver
* Add 8544 SVR numbers to processor.h

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Signed-off-by: Jon Loeliger &lt;jdl@freescale.com&gt;
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<pre>
* Add support to the Makefile
* Add 8544 configuration support to the tsec driver
* Add 8544 SVR numbers to processor.h

Signed-off-by: Ed Swarthout &lt;Ed.Swarthout@freescale.com&gt;
Signed-off-by: Jon Loeliger &lt;jdl@freescale.com&gt;
</pre>
</div>
</content>
</entry>
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