u-boot.git/include/asm-ppc/processor.h, branch v1.3.2 Unnamed repository; edit this file 'description' to name the repository. 85xx: Remove cache config from configs.h 2008-01-09T22:25:04+00:00 Kumar Gala galak@kernel.crashing.org 2008-01-08T07:22:21+00:00 b009f3eca99bb7b9e6ba6639a8909a138dd5e9fe Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Either use the standard defines in asm/cache.h or grab the information
at runtime from the L1CFG SPR.

Also, minor cleanup in cache.h to make the code a bit more readable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Merge commit 'wd/master' 2008-01-03T15:46:55+00:00 Jon Loeliger jdl@freescale.com 2008-01-03T15:46:55+00:00 2c3536425d987bf079258973e2acebaaef3e16b6 






ppc4xx: Define CONFIG_BOOKE for all PPC440 based processors
2007-10-31T20:20:50+00:00

Eugene O'Brien
eugene.obrien@advantechamt.com

2007-10-18T15:29:04+00:00

f6ba9b56607d4b27550301c7c7f6b55b654fd62a

CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR
number is used to access system registers.

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>





CONFIG_BOOKE must be defined for PPC440 processors so that the proper SPR
number is used to access system registers.

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>







ppc4xx: Add PPC405EX support
2007-10-31T20:20:49+00:00

Stefan Roese
sr@denx.de

2007-10-05T15:10:59+00:00

dbbd125721aea6645fdb962f36bd41f59e272f9d

Signed-off-by: Stefan Roese <sr@denx.de>





Signed-off-by: Stefan Roese <sr@denx.de>







Initial mpc8610hpcd cpu/, README and include/ files.
2007-10-17T20:01:47+00:00

Jon Loeliger
jdl@freescale.com

2007-10-16T20:26:51+00:00

9553df86d3a319c3a1a7cde7e4edd6eeb5aa64c7

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>





Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Mahesh Jade <mahesh.jade@freescale.com>
Signed-off-by: Jason Jin <Jason.jin@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>







85xx start.S cleanup and exception support
2007-08-14T06:34:21+00:00

Andy Fleming
afleming@freescale.com

2007-08-14T06:34:21+00:00

61a21e980a7b9188424d04f1c265fdc5c21c7e85

From: Ed Swarthout <Ed.Swarthout@freescale.com>

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>





From: Ed Swarthout <Ed.Swarthout@freescale.com>

Support external interrupts from platform to eliminate system hangs.
Define CONFIG_INTERRUPTS board configure option to enable.
Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC.

Remove extra cpu initialization redundant with hardware initialization.
Whitespace cleanup.

Define and use _START_OFFSET consistent with other processors using
ppc_asm.tmpl

Move additional code from .text to boot page to make room for
exception vectors at start of image.

Handle Machine Check, External and Critical exceptions.

Fix e500 machine check error determination in traps.c

TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>







fsl_pci_init cleanup.
2007-08-10T16:39:37+00:00

Ed Swarthout
Ed.Swarthout@freescale.com

2007-07-27T06:50:45+00:00

2e4d94f1e3c2961428967a33b6ff2520568391b3

Do not enable normal errors created during probe (master abort, perr,
and pcie Invalid Configuration access).

Add CONFIG_PCI_NOSCAN board option to prevent bus scan.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>





Do not enable normal errors created during probe (master abort, perr,
and pcie Invalid Configuration access).

Add CONFIG_PCI_NOSCAN board option to prevent bus scan.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>







cpu/86xx fixes.
2007-08-10T16:02:32+00:00

Jon Loeliger
jdl@freescale.com

2007-08-02T19:42:20+00:00

cfc7a7f5bb3273c9951173c788001d45118f141f

Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>





Remove rev 1 fixes.
Always set PICGCR_MODE.
Enable machine check and provide board config option
to set and handle SoC error interrupts.

Include MSSSR0 in error message.

Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>







[PPC] Remove unused MSR_USER definition
2007-07-27T12:22:04+00:00

Rafal Jaworowski
raj@semihalf.com

2007-07-27T12:22:04+00:00

1863cfb7b100ba0ee3401799457a01dc058745f8

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>





Signed-off-by: Rafal Jaworowski <raj@semihalf.com>







Fix breakage of 8xx boards from recent commit.
2007-07-19T15:12:28+00:00

Rafal Jaworowski
raj@semihalf.com

2007-07-19T15:12:28+00:00

cc3023b9f95d7ac959a764471a65001062aecf41

This patch fixes the negative consequences for 8xx of the recent
"ppc4xx: Clean up 440 exceptions handling" commit.

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>





This patch fixes the negative consequences for 8xx of the recent
"ppc4xx: Clean up 440 exceptions handling" commit.

Signed-off-by: Rafal Jaworowski <raj@semihalf.com>