u-boot.git/include/asm-ppc/processor.h, branch v2010.03

85xx: Fix enabling of L1 cache parity on secondary cores

2010-03-30T15:48:30+00:00

Use the same code between primary and secondary cores to init the
L1 cache.  We were not enabling cache parity on the secondary cores.

Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks.  Than enables the cache and
makes sure its enabled before continuing.

Signed-off-by: Kumar Gala

ppc: Added macro to test for specific SVR revision

2010-01-05T19:49:09+00:00

Various SoC errata are specific to a given revision of silicon. This
patch gives us a simple macro to use when doing such tests.

Signed-off-by: Kumar Gala

ppc4xx: Add PPC405EX(r) Rev D support

2009-10-07T07:14:27+00:00

Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:

0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec

Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.

Signed-off-by: Stefan Roese 
Cc: Phong Vo"

ppc/p4080: Add various p4080 related defines (and p4040)

2009-09-24T17:05:28+00:00

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080

Signed-off-by: Kumar Gala

ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.

2009-09-16T02:30:08+00:00

Its reset value is random, and we sometimes read uninitialized TLB
arrays.  Make sure that we don't retain MAS8 from reading such an entry
if the VF bit in MAS8 is set, attempts to use the mapping will trap.

Signed-off-by: Scott Wood

ppc/85xx,86xx: Handling Unknown SOC version

2009-09-08T14:10:08+00:00

Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

85xx: Add support for setting IVORs to fixed offset defaults

2009-09-08T14:10:05+00:00

In future Book-E implementations IVORs will most likely go away and be
replaced with fixed offsets.  The IVPR will continue to exist to allow
for relocation of the interrupt vectors.

This code adds support to setup the IVORs as their fixed offset values
per the ISA 2.06 spec when we transition from u-boot to another OS
either via 'bootm' or a cpu release.

Signed-off-by: Kumar Gala

85xx: Added single core members of FSL P1xx/P2xx processors series

2009-08-28T22:12:41+00:00

P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

85xx: Added P1020 Processor Support.

2009-08-28T22:12:39+00:00

P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala

8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx

2009-08-28T22:12:38+00:00

The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal 
Signed-off-by: Kumar Gala