u-boot.git/include/asm-ppc, branch master

Move architecture-specific includes to arch/$ARCH/include/asm

2010-04-13T07:13:12+00:00

This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.

Signed-off-by: Peter Tyser

85xx: Set HID1[mbdd] on e500v2 rev5.0 or greater

2010-04-07T05:21:27+00:00

The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize
the performance of mbar/eieio instructions.

Signed-off-by: Sandeep Gopalpet

85xx: Added various P1012/P1013/P1021/P1022 defines

2010-04-07T05:21:22+00:00

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config

Signed-off-by: Haiying Wang 
Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Kumar Gala

85xx: Add defines for BUCSR bits to make code more readable

2010-04-07T05:08:17+00:00

Signed-off-by: Kumar Gala

mpc86xx: set the DDR BATs after calculating true DDR size

2010-03-30T15:50:22+00:00

After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly.  This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.

On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way.  If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation.  The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).

Currently we are limited to power of two sized DDR since we only use a
single bat.  If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.

Signed-off-by: Timur Tabi 
Signed-off-by: Kumar Gala

85xx: Fix enabling of L1 cache parity on secondary cores

2010-03-30T15:48:30+00:00

Use the same code between primary and secondary cores to init the
L1 cache.  We were not enabling cache parity on the secondary cores.

Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks.  Than enables the cache and
makes sure its enabled before continuing.

Signed-off-by: Kumar Gala

PPC: Record U-Boot's relocated address in RAM and show in bdinfo.

2010-03-11T22:49:16+00:00

This patch uses gd->relocaddr variable to store uboot's relocated
address in RAM and shows it in bdinfo command.

This patch moves CONFIG_AMIGAONEG3SE style copying of the address
in board_init_f to just before relocation is actually done.

Signed-off-by: Richard Retanubun 
Tested-by: Detlev Zundel

ppc4xx: Corrected EBC register bit definitions

2010-03-02T13:12:52+00:00

Corrected the bit field positions of the external master priority low
and the external master priority high values in the EBC configuration
register. These bit field positions differ between PPC405 and PPC440
processors

Signed-off-by: Eugene O'Brien 
Signed-off-by: Stefan Roese

86xx: Add support for 'cpu disable' command

2010-01-27T05:17:50+00:00

Support disabling of a core via user command 'cpu disable'.

Signed-off-by: Kumar Gala

lmb: only force on arches that use it

2010-01-21T21:26:00+00:00

Signed-off-by: Mike Frysinger