u-boot.git/include/asm-ppc, branch v2008.10-rc3

Fix the incorrect DDR clk freq reporting on 8536DS

2008-10-07T20:37:08+00:00

On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111),
The display is still sync mode DDR freq. This patch try to fix
this. The display DDR freq is now the actual freq in both
sync and async mode.

Signed-off-by: Jason Jin

ppc4xx: Move ppc4xx specific prototypes to ppc4xx header

2008-09-08T12:11:12+00:00

This patch moves some 4xx specific prototypes out of include common.h
to a ppc4xx specific header.

Signed-off-by: Stefan Roese

Merge branch 'master' of /home/stefan/git/u-boot/u-boot

2008-09-08T08:35:49+00:00

Allow console input to be disabled

2008-09-06T20:36:54+00:00

Added new CONFIG_DISABLE_CONSOLE define and GD_FLG_DISABLE_CONSOLE.

When CONFIG_DISABLE_CONSOLE is defined, setting
GD_FLG_DISABLE_CONSOLE disables all console input and output.

Signed-off-by: Mark Jackson

ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines

2008-09-05T10:04:16+00:00

Signed-off-by: Adam Graham 
Signed-off-by: Stefan Roese

mpc83xx: Store and display Arbiter Event Register values

2008-09-03T21:06:57+00:00

Record the Arbiter Event Register values and optionally display them.

The Arbiter Event Register can record the type and effective address of
an arbiter error, even through an HRESET. This patch stores the values in
the global data structure.

Display of the Arbiter Event registers immediately after the RSR value
can be enabled with defines. The Arbiter values will only be displayed
if an arbiter event has occured since the last Power On Reset, and either
of the following defines exist:
 #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and
                                    and type register values
 #define CONFIG_DISPLAY_AER_FULL  - display and interpret the arbiter
                                    event register values

Address Only transactions are one of the trapped events that can register
as an arbiter event. They occur with some cache manipulation instructions
if the HID0_ABE (Address Broadcast Enable) is set and the memory region
has the MEMORY_COHERENCE WIMG bit set. Setting:
 #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address
                              only events, so that it can still capture
                              other real problems.

Signed-off-by: Nick Spence 
Signed-off-by: Kim Phillips

mpc85xx: Add support for the MPC8536

2008-08-27T16:43:54+00:00

The MPC8536 Adds SDHC and SATA controllers to the PQ3 family.  We
also have SERDES init code for the 8536.

Signed-off-by: Kumar Gala 
Signed-off-by: Srikanth Srinivasan 
Signed-off-by: Dejan Minic 
Signed-off-by: Jason Jin 
Signed-off-by: Dave Liu

FSL DDR: Add e500 TLB helper for DDR code

2008-08-27T16:43:48+00:00

Provide a helper function that board code can call to map TLBs when
setting up DDR.

Signed-off-by: Kumar Gala

FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.

2008-08-27T00:05:58+00:00

The main purpose of this rewrite it to be able to share the same
initialization code on all FSL PowerPC products that have DDR
controllers.  (83xx, 85xx, 86xx).

The code is broken up into the following steps:
	GET_SPD
	COMPUTE_DIMM_PARMS
	COMPUTE_COMMON_PARMS
	GATHER_OPTS
	ASSIGN_ADDRESSES
	COMPUTE_REGS
	PROGRAM_REGS

This allows us to share more code an easily allow for board specific code
overrides.

Additionally this code base adds support for >4G of DDR and provides a
foundation for supporting interleaving on processors with more than one
controller.

Signed-off-by: James Yang 
Signed-off-by: Jon Loeliger 
Signed-off-by: Becky Bruce 
Signed-off-by: Ed Swarthout 
Signed-off-by: Kumar Gala

FSL DDR: Provide a generic set_ddr_laws()

2008-08-27T00:05:55+00:00

Provide a helper function that will setup the last available
LAWs (upto 2) for DDR.  Useful for SPD/dyanmic DDR setting code.

Signed-off-by: Kumar Gala