u-boot.git/include/asm-ppc, branch v2010.03-rc2 Unnamed repository; edit this file 'description' to name the repository. PPC: Record U-Boot's relocated address in RAM and show in bdinfo. 2010-03-11T22:49:16+00:00 Richard Retanubun RichardRetanubun@RuggedCom.com 2010-01-15T15:06:06+00:00 4b99327a4121a28d2bdb2c2b841f5d97931ae905 This patch uses gd->relocaddr variable to store uboot's relocated address in RAM and shows it in bdinfo command. This patch moves CONFIG_AMIGAONEG3SE style copying of the address in board_init_f to just before relocation is actually done. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Tested-by: Detlev Zundel <dzu@denx.de> 
This patch uses gd->relocaddr variable to store uboot's relocated
address in RAM and shows it in bdinfo command.

This patch moves CONFIG_AMIGAONEG3SE style copying of the address
in board_init_f to just before relocation is actually done.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Tested-by: Detlev Zundel <dzu@denx.de>
ppc4xx: Corrected EBC register bit definitions 2010-03-02T13:12:52+00:00 Eugene O'Brien eugene.g.obrien@gmail.com 2010-02-24T19:10:24+00:00 87800f72414b830756aefc757dd191688febacf9 Corrected the bit field positions of the external master priority low and the external master priority high values in the EBC configuration register. These bit field positions differ between PPC405 and PPC440 processors Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de> 
Corrected the bit field positions of the external master priority low
and the external master priority high values in the EBC configuration
register. These bit field positions differ between PPC405 and PPC440
processors

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
Signed-off-by: Stefan Roese <sr@denx.de>
86xx: Add support for 'cpu disable' command 2010-01-27T05:17:50+00:00 Kumar Gala galak@kernel.crashing.org 2010-01-12T17:51:52+00:00 c894852b7aa2ac5f04ca70a073f803aa665c3ec1 Support disabling of a core via user command 'cpu disable'. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Support disabling of a core via user command 'cpu disable'.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
lmb: only force on arches that use it 2010-01-21T21:26:00+00:00 Mike Frysinger vapier@gentoo.org 2009-11-03T16:35:59+00:00 a16028da63c78001823bfb375b3f6d9d86e5a534 Signed-off-by: Mike Frysinger <vapier@gentoo.org> 
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
ppc/p4080: Add Corenet Platform Cache (CPC) registers 2010-01-05T19:52:00+00:00 Becky Bruce beckyb@kernel.crashing.org 2009-11-18T03:10:21+00:00 8b0ab304943b07d13a29db6d3d2ca3edad32cdcb Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
fsl-ddr: add override for the Rtt_Wr 2010-01-05T19:49:27+00:00 Dave Liu daveliu@freescale.com 2009-12-16T16:24:38+00:00 1aa3d08a0244506b94031522e54fe06ee7a5ae0e Different boards may require different settings of Dynamic ODT (Rtt_Wr). We provide a means to allow the board specific code to provide its own value of Rtt_Wr. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
fsl-ddr: add the override for write leveling 2010-01-05T19:49:10+00:00 Dave Liu daveliu@freescale.com 2009-12-16T16:24:37+00:00 bdc9f7b5eab8d5edd8a8cc5d80ef080836b00e85 add the override for write leveling sampling and start time according to specific board. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
add the override for write leveling sampling and
start time according to specific board.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
fsl_law: add SRIO2 target id and law_size_bits() macro 2010-01-05T19:49:09+00:00 Li Yang leoli@freescale.com 2009-12-09T06:26:08+00:00 de3cbd78c9a485389b233f8ca705a9e5f51afaf3 Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ppc: Added macro to test for specific SVR revision 2010-01-05T19:49:09+00:00 Kumar Gala galak@kernel.crashing.org 2009-11-18T04:44:52+00:00 effe4973f2f349e6e87d455ae718aabaf919a75d Various SoC errata are specific to a given revision of silicon. This patch gives us a simple macro to use when doing such tests. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Various SoC errata are specific to a given revision of silicon. This
patch gives us a simple macro to use when doing such tests.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
ppc/85xx: Add tracking of TLB CAM usage 2010-01-05T19:49:08+00:00 Kumar Gala galak@kernel.crashing.org 2009-11-12T16:26:16+00:00 94e9411b9dda182dd63d53ba6ea640c98b35db5f We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code.  For example the SPD
DDR code today hard codes which TLB entries it uses.  We can now make
that pick entries that are free.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>