u-boot.git/include/clk, branch v2023.01

reset: sunxi: Reuse the platform data from the clock driver

2022-07-18T08:37:50+00:00

The clock and reset drivers use the exact same platform data. Simplify
them by sharing the object. This is safe because the parent device
(the clock device) always gets its driver model callbacks run first.

Signed-off-by: Samuel Holland 
Acked-by: Andre Przywara 
Signed-off-by: Andre Przywara

clk: sunxi: Convert driver private data to platform data

2022-07-18T08:37:50+00:00

All of the driver private data should really be platform data since it
is determined statically (selected by the compatible string or extracted
from the devicetree). Move everything to platform data, so it can be
provided when binding the driver. This is useful for SPL, or for
instantiating the driver as part of an MFD.

Signed-off-by: Samuel Holland 
Reviewed-by: Andre Przywara 
Signed-off-by: Andre Przywara

clk: sunxi: Use a single driver for all variants

2022-07-18T08:37:49+00:00

Now that all of the variants use the same bind/probe functions and ops,
there is no need to have a separate driver for each variant. Since most
SoCs contain two variants (the main CCU and PRCM CCU), this saves a bit
of firmware size and RAM.

Signed-off-by: Samuel Holland 
Reviewed-by: Andre Przywara 
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara

reset: sunxi: Get the reset count from the CCU descriptor

2022-07-18T08:37:49+00:00

This allows all of the clock drivers to use a common bind function.

Signed-off-by: Samuel Holland 
Reviewed-by: Andre Przywara 
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara

clk: sunxi: Store the array sizes in the CCU descriptor

2022-07-18T08:37:49+00:00

The reset array size is currently used for bounds checking in the reset
driver. The same bounds check should really be done in the clock driver.

Currently, the array size is provided to the reset driver separately
from the CCU descriptor, which is a bit strange. Let's do this the usual
way, with the array sizes next to the arrays themselves.

Signed-off-by: Samuel Holland 
Reviewed-by: Andre Przywara 
[Andre: add F1C100s support]
Signed-off-by: Andre Przywara

clk: sunxi: add and use dummy gate clocks

2022-05-24T00:16:15+00:00

Some devices enumerate various clocks in their DT, and many drivers
just blanketly try to enable all of them. This creates problems
since we only model a few gate clocks, and the clock driver outputs
a warning when a clock is not described:
=========
sunxi_set_gate: (CLK#3) unhandled
=========

Some clocks don't have an enable bit, or are already enabled in a
different way, so we might want to just ignore them.

Add a CCU_CLK_F_DUMMY_GATE flag that indicates that case, and define
a GATE_DUMMY macro that can be used in the clock description array.
Define a few clocks, used by some pinctrl devices, that way to suppress
the runtime warnings.

Signed-off-by: Andre Przywara 
Reviewed-by: Samuel Holland

doc: replace @return by Return:

2022-01-19T17:11:34+00:00

Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt

clk: sunxi: Move header out of arch directory

2021-10-11T09:46:44+00:00

The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.

Signed-off-by: Samuel Holland 
Reviewed-by: Bin Meng 
Signed-off-by: Andre Przywara