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<title>u-boot.git/include/configs/coreboot.h, branch v2013.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>x86: config: Add tracing options</title>
<updated>2013-06-26T14:18:56+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-06-11T18:14:53+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b5f319373400d3c7e6820e793a7bb370ad0c8a76'/>
<id>b5f319373400d3c7e6820e793a7bb370ad0c8a76</id>
<content type='text'>
Add configs to enable tracing when it is needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Add configs to enable tracing when it is needed.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: config: Reflect the name changes of LPC TPM configs</title>
<updated>2013-06-03T08:26:25+00:00</updated>
<author>
<name>Tom Wai-Hong Tam</name>
<email>waihong@chromium.org</email>
</author>
<published>2013-04-12T11:04:35+00:00</published>
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<id>5bdf46b71b26263d090ccdb1c6679afd085f0323</id>
<content type='text'>
The new name is more aligned with Linux kernel's naming of TPM driver.

Signed-off-by: Tom Wai-Hong Tam &lt;waihong@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
The new name is more aligned with Linux kernel's naming of TPM driver.

Signed-off-by: Tom Wai-Hong Tam &lt;waihong@chromium.org&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>x86: config: Enable LZO for coreboot, remove zlib, gzip</title>
<updated>2013-05-13T20:33:22+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-04-17T16:13:46+00:00</published>
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<id>04dbf77d6275ce7bfba748c603957b0ebbb07b64</id>
<content type='text'>
We don't use zlib and gzip but do use lzo, so enable this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
We don't use zlib and gzip but do use lzo, so enable this.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Enable bootstage for coreboot</title>
<updated>2013-05-13T20:33:21+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-04-17T16:13:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2e65959be679a2401b0f0fc02934f6b6d48f9fd8'/>
<id>2e65959be679a2401b0f0fc02934f6b6d48f9fd8</id>
<content type='text'>
This is a convenient way of finding out where boottime is going. Enable
it for coreboot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
This is a convenient way of finding out where boottime is going. Enable
it for coreboot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Re-enable PCAT timer 2 for beeping</title>
<updated>2013-05-13T20:33:21+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-04-17T16:13:39+00:00</published>
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<id>d0b6f247a1e7ffd06d931ca4088426134dc4e546</id>
<content type='text'>
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Add TSC timer</title>
<updated>2013-05-13T20:33:21+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-04-17T16:13:36+00:00</published>
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<id>e761ecdbb83e3151ffea5b531523256c57e62527</id>
<content type='text'>
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.

Tidy up some old broken and unneeded implementations at the same time.

To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;base
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.

Tidy up some old broken and unneeded implementations at the same time.

To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;base
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: config: Init PCI before SPI</title>
<updated>2013-04-15T23:26:43+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-04-15T11:25:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=617c246f3c123d4a2d4dba9d08a4a2dd324cb407'/>
<id>617c246f3c123d4a2d4dba9d08a4a2dd324cb407</id>
<content type='text'>
Since the ICH SPI controller uses PCI, we must ensure that PCI is available
before it is inited.

This fixes the current "ICH SPI: Cannot find device" message on boot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Since the ICH SPI controller uses PCI, we must ensure that PCI is available
before it is inited.

This fixes the current "ICH SPI: Cannot find device" message on boot.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'spi' of git://git.denx.de/u-boot-x86</title>
<updated>2013-03-20T18:55:10+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2013-03-20T18:55:10+00:00</published>
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<id>8b906a9f0b3fd0d4421e08c4fa62f61a01289611</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>x86: Enable time command for coreboot</title>
<updated>2013-03-19T15:45:37+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-03-11T06:08:12+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=363464f9939633bd0dd5516e486e791bb395c745'/>
<id>363464f9939633bd0dd5516e486e791bb395c745</id>
<content type='text'>
This command is useful for measuring SPI flash load times and the like.
Enable gettime as well to obtain absolute time tick values.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
This command is useful for measuring SPI flash load times and the like.
Enable gettime as well to obtain absolute time tick values.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Enable SPI flash support for coreboot</title>
<updated>2013-03-19T15:45:37+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2013-03-11T06:08:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e30bd5cfee742b93de8e6794a1f896ee501ef738'/>
<id>e30bd5cfee742b93de8e6794a1f896ee501ef738</id>
<content type='text'>
Turn on SPI flash support and related commands.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Turn on SPI flash support and related commands.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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