u-boot.git/include/configs/coreboot.h, branch v2013.10 Unnamed repository; edit this file 'description' to name the repository. Coding Style cleanup: remove trailing white space 2013-10-14T20:06:53+00:00 Wolfgang Denk wd@denx.de 2013-10-07T11:07:26+00:00 3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7 Signed-off-by: Wolfgang Denk <wd@denx.de> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
ahci: convert to use libata functions and definitions 2013-09-06T17:09:07+00:00 Rob Herring rob.herring@calxeda.com 2013-08-24T15:10:54+00:00 344ca0b40cf3a8feb1e7f9d4ff9e5041be706266 libata already has similar functions as implemented in the ahci code. Refactor the code to use the libata variants and remove the dependency on ata.h. Convert some defines to use the version from libata.h. Also, remove some unnecessary memset's of bss data. This is a step toward hopefully merging ahci.c and dw_ahsata.c which are essentially the same driver. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Tom Rini <trini@ti.com> 
libata already has similar functions as implemented in the ahci code.
Refactor the code to use the libata variants and remove the dependency on
ata.h. Convert some defines to use the version from libata.h. Also, remove
some unnecessary memset's of bss data.

This is a step toward hopefully merging ahci.c and dw_ahsata.c which are
essentially the same driver.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Tom Rini <trini@ti.com>
Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24T13:44:38+00:00 Wolfgang Denk wd@denx.de 2013-07-08T07:37:19+00:00 1a4596601fd395f3afb8f82f3f840c5e00bdd57a Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com> 
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
x86: config: Add tracing options 2013-06-26T14:18:56+00:00 Simon Glass sjg@chromium.org 2013-06-11T18:14:53+00:00 b5f319373400d3c7e6820e793a7bb370ad0c8a76 Add configs to enable tracing when it is needed. Signed-off-by: Simon Glass <sjg@chromium.org> 
Add configs to enable tracing when it is needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: config: Reflect the name changes of LPC TPM configs 2013-06-03T08:26:25+00:00 Tom Wai-Hong Tam waihong@chromium.org 2013-04-12T11:04:35+00:00 5bdf46b71b26263d090ccdb1c6679afd085f0323 The new name is more aligned with Linux kernel's naming of TPM driver. Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> 
The new name is more aligned with Linux kernel's naming of TPM driver.

Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
x86: config: Enable LZO for coreboot, remove zlib, gzip 2013-05-13T20:33:22+00:00 Simon Glass sjg@chromium.org 2013-04-17T16:13:46+00:00 04dbf77d6275ce7bfba748c603957b0ebbb07b64 We don't use zlib and gzip but do use lzo, so enable this. Signed-off-by: Simon Glass <sjg@chromium.org> 
We don't use zlib and gzip but do use lzo, so enable this.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Enable bootstage for coreboot 2013-05-13T20:33:21+00:00 Simon Glass sjg@chromium.org 2013-04-17T16:13:43+00:00 2e65959be679a2401b0f0fc02934f6b6d48f9fd8 This is a convenient way of finding out where boottime is going. Enable it for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> 
This is a convenient way of finding out where boottime is going. Enable
it for coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Re-enable PCAT timer 2 for beeping 2013-05-13T20:33:21+00:00 Simon Glass sjg@chromium.org 2013-04-17T16:13:39+00:00 d0b6f247a1e7ffd06d931ca4088426134dc4e546 While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> 
While we don't want PCAT timers for timing, we want timer 2 so that we can
still make a beep. Re-purpose the PCAT driver for this, and enable it in
coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Add TSC timer 2013-05-13T20:33:21+00:00 Simon Glass sjg@chromium.org 2013-04-17T16:13:36+00:00 e761ecdbb83e3151ffea5b531523256c57e62527 This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing. Tidy up some old broken and unneeded implementations at the same time. To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time. Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org> 
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.

Tidy up some old broken and unneeded implementations at the same time.

To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.

Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: config: Init PCI before SPI 2013-04-15T23:26:43+00:00 Simon Glass sjg@chromium.org 2013-04-15T11:25:21+00:00 617c246f3c123d4a2d4dba9d08a4a2dd324cb407 Since the ICH SPI controller uses PCI, we must ensure that PCI is available before it is inited. This fixes the current "ICH SPI: Cannot find device" message on boot. Signed-off-by: Simon Glass <sjg@chromium.org> 
Since the ICH SPI controller uses PCI, we must ensure that PCI is available
before it is inited.

This fixes the current "ICH SPI: Cannot find device" message on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>