u-boot.git/include/configs/mx6_common.h, branch v2015.04

mx6_common: Do not select esdhc DDR mode for all boards

2015-03-13T12:35:12+00:00

CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE should be selected only by boards that really
have a DDR-capable eMMC, so remove this option from common code to avoid
regressions.

Reported-by: Stefan Roese 
Signed-off-by: Fabio Estevam 
Acked-by: Otavio Salvador 
Reviewed-by: Volodymyr Riazantsev 
Tested-by: Stefan Roese

mmc: fsl_esdhc: Add support for DDR mode

2015-02-24T21:11:10+00:00

Add support of the DDR mode for eSDHC driver.
Enable it for i.MX6 SoC family only.

Signed-off-by: Volodymyr Riazantsev 
Reviewed-by: York Sun

imx: mx6: Enable high frequency clock source for GPT

2014-11-03T10:21:49+00:00

Set the CONFIG_MXC_GPT_HCLK configuration in mx6_common.h, so that
24Mhz OSC clock source will be selected for GPT on all MX6 platforms.

Signed-off-by: Ye.Li

mx6: add support of multi-processor command

2014-08-20T09:52:54+00:00

This allows u-boot to load different OS or Bare Metal application on
different cores of the i.MX6 SoC.
For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1.

Signed-off-by: Gabriel Huau 
Acked-by: Stefano Babic

mx6: drop ARM errata 742230

2014-06-17T14:33:24+00:00

Commit e9fd66defd7e (ARM: mx6: define CONFIG_ARM_ERRATA_742230) enables
errata 742230 for imx6, because it helps remove one reboot issue.
However, this errata does not really apply on imx6, because Cortex-A9
on imx6 is r2p10 while the errata only applies to revisions r1p0..r2p2.

At a later time, commit f71cbfe3ca5d (ARM: Add workaround for Cortex-A9
errata 794072) adds support of errata 794072, which applies to all
Cortex-A9 revisions.  As the workaround for both errata are exactly
same, it makes a lot more sense to select 794072 instead of 742230 for
imx6.  Since we already enable 794072 for imx6, it's time to drop
errata 742230 to avoid confusion.

Signed-off-by: Shawn Guo 
Acked-by: Nitin Garg

MX6: Enable ARM errata workaround 794072 and 761320

2014-04-07T16:11:01+00:00

Since MX6 is Cortex-A9 r2p10, enable software workaround
for errata 794072 and 761320.

Signed-off-by: Nitin Garg

mx6: Enable L2 cache support

2014-02-11T10:24:12+00:00

Add L2 cache support and enable it by default.

Configure the L2 cache in the same way as done by FSL kernel:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_4.1.0

Signed-off-by: Fabio Estevam 
Acked-by: Dirk Behme 
Acked-by: Stefano Babic

mx6: soc: Add the required LDO ramp up delay

2014-01-02T16:16:51+00:00

When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.

Signed-off-by: Fabio Estevam

ARM: mx6: define CONFIG_ARM_ERRATA_742230

2013-04-17T08:19:29+00:00

The ARM errata 742230 - "ARM errata: DMB operation may be faulty" is
claimed for Cortex-A9 (r1p0..r2p2).  Though i.MX6 uses a newer revision
than r2p2, we are seeing a reboot failure on i.MX6 SMP build that can be
fixed by applying the workaround for this errata.  So for safety, let's
define CONFIG_ARM_ERRATA_742230 to enable the workaround on i.MX6.

Signed-off-by: Shawn Guo

ARM: mx6: use common CPU errata config options

2013-03-07T17:20:37+00:00

Now that U-Boot has common CONFIG_ options to work around some ARM CPU
errata, enable the relevant options on MX6, and remove the custom
lowlevel_init.S, since it's just duplicated code now.

Signed-off-by: Stephen Warren 
Reviewed-by: Fabio Estevam 
Acked-by: Jason Liu