A newer CPLD version on the 405EX evaluation board requires a different
EBC controller setup for the CPLD register access. This patch adds a CPLD
version detection for Kilauea and code to reconfigure the EBC controller
(chip select 2) for the old CPLD if no new version is found.

Additionally the CPLD version is printed upon bootup:

Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0)

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Cc: Zhang Bao Quan <bqzhang@udtech.com.cn>

Neither the MVBLUE nor its underlying architecture implement the
do_irqinfo() function which is required when CONFIG_CMD_IRQ is defined.
This change fixes the following MVBLUE compiler error:

-> ./MAKEALL MVBLUE
Configuring for MVBLUE board...
common/libcommon.a(cmd_irq.o):(.u_boot_cmd+0x24): undefined reference to `do_irqinfo'
make: *** [u-boot] Error 1

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Andre Schwarz <andre.schwarz@matrix-vision.de>

The support for this was silently dropped by a configuration
split during the merge of the imx27lite board support in commit
864aa034f3a0e10ce710e8bbda171df3cab59414 (cmd_mtdparts: Move to common
handling of FLASH devices via MTD layer).

Signed-off-by: Detlev Zundel <dzu@denx.de>

A typo caused the stack and malloc regions to overlap, which prevented
mem_malloc_init() from returning. This commit makes the memory layout match
the example described in include/configs/microblaze-generic.h

Signed-off-by: Graeme Smecher <graeme.smecher@mail.mcgill.ca>
Signed-off-by: Michal Simek <monstr@monstr.eu>

A bunch of the 85xx boards have this cruft in them - it's not used
anywhere.  Delete it.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>

This patch adds a default bootargs "fbmem" value to the
CONFIG_BOOTARGS string for the MIMC200 board.

Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>

This patch fixes an ugly behavior of the IL712 magnetic couplers
as used on PLU405. These parts will remember their last state
over a power cycle which might cause unwanted behavior.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>

Both lpd7a400 and lpd7a404 failed to compile because they had
CONFIG_SMC_USE_IOFUNCS defined:

examples/standalone/smc91111_eeprom.c:388: undefined reference to `SMC_outw'

Also removed an orphaned paren in lpd7a404.h

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>

This patch fixes a problem only seen very occasionally on Canyonlands.
The NOR flash interface (CFI driver) doesn't work reliably in all cases.
Erasing and/or programming sometimes doesn't work. Sometimes with
an error message, like "flash not erased" when trying to program an
area that should have just been erased. And sometimes without any error
messages. As mentioned above, this problem was only seen rarely and with
some PLL configuration (CPU speed, EBC speed).

Now I spotted this problem a few times, when running my Canyonlands with
the following setup (chip_config):

1000-nor         - NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100

Changing the EBC configuration to not release the bus into high
impedance state inbetween the transfers (ATC, DTC and CTC bits set to 1
in EBC0_CFG) seems to fix this problem. I haven't seen any failure
anymore with this patch applied.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: David Mitchell <dmitchell@amcc.com>
Cc: Jeff Mann <MannJ@embeddedplanet.com>