u-boot.git/include/configs, branch v2014.10-rc3

Merge branch 'master' of git://git.denx.de/u-boot-usb

2014-10-06T19:49:50+00:00

arm: socfpga: Use CMD_FS_GENERIC

2014-10-06T15:46:51+00:00

Enable and use the CONFIG_CMD_FS_GENERIC to avoid hard-coding the
filesystem type into the environment.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Pavel Machek

arm: socfpga: Split SoCFPGA configuration

2014-10-06T15:46:51+00:00

Split the SoCFPGA configuration into SoC-specific part which is
common for all boards (socfpga_cyclone5_common.h) and a board
specific part. There is currently only one board, which is the
generic SoCFPGA board (socfpga_cyclone5.h), but there are more
to come.

This is necessary due to various features of the boards, which
unfortunatelly cannot be autodetected.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Pavel Machek

arm: socfpga: Clean up SoCFPGA configuration

2014-10-06T15:46:51+00:00

Reorganize and cleanup the configuration file for SoCFPGA. There
is no functional change after this cleanup. This was necessary,
since the file was a wild mess and it was impossible to make sense
of it's content, let alone change something without breaking some
other thing. This patch puts the contents on par with regular U-Boot
standards.

Also remove unused preprocessor symbols CONFIG_SINGLE_BOOTOADER
and CONFIG_USE_IRQ, which is undefined by default. Finally, do
logical reordering of the defines in the file so it's much more
readable. The reordering was also necessary for the splitting
as the initial one was messy.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek

arm: socfpga: Enable SDMMC boot for SOCFPGA U-Boot

2014-10-06T15:46:51+00:00

Enable the SDMMC boot as default boot for SOCFPGA U-Boot dev kit.
Enable the bootz command as zImage is used instead uImage.

Signed-off-by: Chin Liang See 
Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Tom Rini 
Cc: Albert Aribaud 
Cc: Wolfgang Denk 
Acked-by: Pavel Machek

arm: socfpga: Enable DWMMC for SOCFPGA

2014-10-06T15:46:51+00:00

Enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit

Signed-off-by: Chin Liang See 
Signed-off-by: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Pavel Machek 
Cc: Marek Vasut 
Cc: Tom Rini 
Cc: Albert Aribaud 
Cc: Wolfgang Denk 
Acked-by: Pavel Machek

arm: socfpga: cache: Enable PL310 L2 cache

2014-10-06T15:46:50+00:00

Enable the PL310 L2 cache controller support for the SoCFPGA.
With the cache related issues resolved, this is safe to be done.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Pavel Machek

arm: socfpga: cache: Enable D-Cache

2014-10-06T15:46:50+00:00

The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Pavel Machek

arm: socfpga: cache: Define cacheline size

2014-10-06T15:46:50+00:00

The Cortex-A9 has 32-byte long L1 cachelines. Define this value.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Pavel Machek

arm: socfpga: timer: Pull the timer reload value from config file

2014-10-06T15:46:49+00:00

The timer reload value is a property of the timer hardware and there
is no reason for this to be configurable. Place this into the timer
driver just like on the other hardware.

Signed-off-by: Marek Vasut 
Cc: Chin Liang See 
Cc: Dinh Nguyen 
Cc: Albert Aribaud 
Cc: Tom Rini 
Cc: Wolfgang Denk 
Cc: Pavel Machek 
Acked-by: Dinh Nguyen 
Acked-by: Pavel Machek