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<title>u-boot.git/include/configs, branch v2018.09-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>x86: efi: payload: Turn on acpi in the kernel command line</title>
<updated>2018-08-30T03:23:14+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-08-23T15:24:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a0913cdf7b7ef1a9f622294cf7a9e97ea9eb72f2'/>
<id>a0913cdf7b7ef1a9f622294cf7a9e97ea9eb72f2</id>
<content type='text'>
Now that we have full Linux kernel boot support on EFI payload,
avoid pass "acpi=off" to the kernel command line.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Now that we have full Linux kernel boot support on EFI payload,
avoid pass "acpi=off" to the kernel command line.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-socfpga</title>
<updated>2018-08-24T20:11:12+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-08-24T20:11:12+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a376702f761be51227bfc8d0ae06722ec40687d8'/>
<id>a376702f761be51227bfc8d0ae06722ec40687d8</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>ARM: display5: Remove "factory procedure" from display5 board config</title>
<updated>2018-08-24T17:20:32+00:00</updated>
<author>
<name>Lukasz Majewski</name>
<email>lukma@denx.de</email>
</author>
<published>2018-08-20T14:23:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=144c4e37db2adb1c296ab36467288a97885aff5a'/>
<id>144c4e37db2adb1c296ab36467288a97885aff5a</id>
<content type='text'>
This code now is regarded as dead one and hence shall be removed.

Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
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<pre>
This code now is regarded as dead one and hence shall be removed.

Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: socfpga: Convert Arria10 to timer framework</title>
<updated>2018-08-24T10:05:20+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@denx.de</email>
</author>
<published>2018-08-18T14:00:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=331c37221057e6a1291b6e14d9f033a7a90051f1'/>
<id>331c37221057e6a1291b6e14d9f033a7a90051f1</id>
<content type='text'>
Switch the Arria10 from ad-hoc hardcoded timer to timer framework
and the DW APB timer driver. This allows the A10 to extract timer
information, like timer rate, from clock framework and thus DT
instead of having it hardcoded in U-Boot configuration files.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;chin.liang.see@intel.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</content>
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<pre>
Switch the Arria10 from ad-hoc hardcoded timer to timer framework
and the DW APB timer driver. This allows the A10 to extract timer
information, like timer rate, from clock framework and thus DT
instead of having it hardcoded in U-Boot configuration files.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Chin Liang See &lt;chin.liang.see@intel.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: Ley Foon Tan &lt;ley.foon.tan@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: layerscape: Build u-boot-with-spl.bin for selected boards</title>
<updated>2018-08-23T15:17:35+00:00</updated>
<author>
<name>Jagdish Gediya</name>
<email>jagdish.gediya@nxp.com</email>
</author>
<published>2018-08-23T17:23:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4b5892c4808ec162253b4b8173b6995e5dac4246'/>
<id>4b5892c4808ec162253b4b8173b6995e5dac4246</id>
<content type='text'>
This patch reverts the changes made for ls1088a and ls2080a
based boards in commit 18b6dd6cb0564 ("armv8: layerscape: Drop
u-boot-with-spl.bin for selected boards").

u-boot-with-spl.bin is required for Gen3 based SoC where internal
ROM copy data in the internal memory

CC: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
CC: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
CC: Pramod Kumar &lt;pramod.kumar_1@nxp.com&gt;
CC: Ashish Kumar &lt;ashish.kumar@nxp.com&gt;
CC: York Sun &lt;york.sun@nxp.com&gt;
Signed-off-by: Jagdish Gediya &lt;jagdish.gediya@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</content>
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<pre>
This patch reverts the changes made for ls1088a and ls2080a
based boards in commit 18b6dd6cb0564 ("armv8: layerscape: Drop
u-boot-with-spl.bin for selected boards").

u-boot-with-spl.bin is required for Gen3 based SoC where internal
ROM copy data in the internal memory

CC: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
CC: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
CC: Pramod Kumar &lt;pramod.kumar_1@nxp.com&gt;
CC: Ashish Kumar &lt;ashish.kumar@nxp.com&gt;
CC: York Sun &lt;york.sun@nxp.com&gt;
Signed-off-by: Jagdish Gediya &lt;jagdish.gediya@nxp.com&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
Reviewed-by: York Sun &lt;york.sun@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge git://git.denx.de/u-boot-x86</title>
<updated>2018-08-20T17:41:37+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2018-08-20T17:41:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3313e908445f7cd7d362955c9054ddf7615d53ef'/>
<id>3313e908445f7cd7d362955c9054ddf7615d53ef</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>display5: Introduce fitImg_fw_sz variable</title>
<updated>2018-08-20T17:11:08+00:00</updated>
<author>
<name>Lukasz Majewski</name>
<email>lukma@denx.de</email>
</author>
<published>2018-08-18T20:22:07+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f008e2600841ff24986fd2b25a8d7498a41f0438'/>
<id>f008e2600841ff24986fd2b25a8d7498a41f0438</id>
<content type='text'>
This cosmetic change allow easy adjustment of the to-load kernel size if
needed.

Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</content>
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<pre>
This cosmetic change allow easy adjustment of the to-load kernel size if
needed.

Reviewed-by: Fabio Estevam &lt;fabio.estevam@nxp.com&gt;
Signed-off-by: Lukasz Majewski &lt;lukma@denx.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Remove support for Advantech SOM-6896</title>
<updated>2018-08-20T05:52:49+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-08-10T09:39:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6e71a6ab2d9e06a275e40a8c5c8e0b29cf6bb8fb'/>
<id>6e71a6ab2d9e06a275e40a8c5c8e0b29cf6bb8fb</id>
<content type='text'>
Now that we have generic coreboot payload support, remove the
dedicated support for Advantech SOM-6896.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
Now that we have generic coreboot payload support, remove the
dedicated support for Advantech SOM-6896.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: coreboot: Add generic coreboot payload support</title>
<updated>2018-08-20T05:52:06+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2018-08-10T09:39:33+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ceeee8f7b5f10d7736840b169249e891da0f6a47'/>
<id>ceeee8f7b5f10d7736840b169249e891da0f6a47</id>
<content type='text'>
Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.

But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Currently building U-Boot as the coreboot payload requires user
to change the build configuration for a specific board during
menuconfig process. This uses the board's native device tree
to configure the hardware. For example, the device tree provides
PCI address range for the PCI host controller and U-Boot will
re-program all PCI devices' BAR to be within this range. In order
to make sure we don't mess up the hardware, we should guarantee
the range matches what coreboot programs the chipset.

But we really should make the coreboot payload support easier.
Just like EFI payload, we can create a generic coreboot payload
for all x86 boards as well. The payload is configured to include
as many generic drivers as possible. All stuff that touches low
level initialization are not allowed as such is the coreboot's
responsibility. Platform specific drivers (like gpio, spi, etc)
are not included.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Christian Gmeiner &lt;christian.gmeiner@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>env: Merge Rockchip, Sunxi, Zynq and ZynqMP</title>
<updated>2018-08-19T16:14:38+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2018-07-19T06:45:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4aee624c927519fc9edc79ccc247486ac3f68392'/>
<id>4aee624c927519fc9edc79ccc247486ac3f68392</id>
<content type='text'>
There is no reason to have the same Kconfig options for different SoCs
separately. The patch is merging them together.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
[trini: Fix ENV_SIZE around ENV_IS_NOWHERE]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
There is no reason to have the same Kconfig options for different SoCs
separately. The patch is merging them together.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
[trini: Fix ENV_SIZE around ENV_IS_NOWHERE]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
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