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<title>u-boot.git/include/configs, branch v2021.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>socfpga64: Do not define CONFIG_SYS_MEM_RESERVE_SECURE to 0</title>
<updated>2021-06-23T12:45:03+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-06-03T13:39:01+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=640e2cd6d4335bd1ec39d284cc913c3b90d608f0'/>
<id>640e2cd6d4335bd1ec39d284cc913c3b90d608f0</id>
<content type='text'>
Based on the comment in socfpga_soc64_common.h, the intention is for
CONFIG_SYS_MEM_RESERVE_SECURE to be unused.  However, in the code we do:
...

and that will evaluate to true.  This leads to unwanted code being
compiled.  Further, as CONFIG_SYS_MEM_RESERVE_SECURE has not been
migrated to Kconfig, this leads to a mismatch in the size of gd
depending on if we have or have not also had &lt;configs/BOARD.h&gt; also
included yet.

Remove the define as it's not needed.

Cc: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
Cc: Chee Hong Ang &lt;chee.hong.ang@intel.com&gt;
Cc: Dalon Westergreen &lt;dalon.westergreen@intel.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
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<pre>
Based on the comment in socfpga_soc64_common.h, the intention is for
CONFIG_SYS_MEM_RESERVE_SECURE to be unused.  However, in the code we do:
...

and that will evaluate to true.  This leads to unwanted code being
compiled.  Further, as CONFIG_SYS_MEM_RESERVE_SECURE has not been
migrated to Kconfig, this leads to a mismatch in the size of gd
depending on if we have or have not also had &lt;configs/BOARD.h&gt; also
included yet.

Remove the define as it's not needed.

Cc: Siew Chin Lim &lt;elly.siew.chin.lim@intel.com&gt;
Cc: Chee Hong Ang &lt;chee.hong.ang@intel.com&gt;
Cc: Dalon Westergreen &lt;dalon.westergreen@intel.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq</title>
<updated>2021-06-17T12:44:56+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-06-17T12:44:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a298d4fbcdba1b38e48ea2af0fc5386cab2070da'/>
<id>a298d4fbcdba1b38e48ea2af0fc5386cab2070da</id>
<content type='text'>
- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
  mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.
</content>
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<pre>
- fsl-qoriq: Bug fixes related pfe, eth, thermal node, vid.c, cpu release,
  mmc, usb, env, etc for Layerscape boards
- powerpc: Update Maintainers for some boards.
</pre>
</div>
</content>
</entry>
<entry>
<title>board: freescale: t208xrdb: add Linux fdt fix-ups for rev D</title>
<updated>2021-06-17T06:16:11+00:00</updated>
<author>
<name>Camelia Groza</name>
<email>camelia.groza@nxp.com</email>
</author>
<published>2021-06-16T12:17:31+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4e21a555c1dc2eacee9e3ad07f3b112c20b0f7a2'/>
<id>4e21a555c1dc2eacee9e3ad07f3b112c20b0f7a2</id>
<content type='text'>
The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs
connected to MAC1 and MAC2. The second Aquantia PHY is located at a
different address on the MDIO bus compared to rev C (0x8 instead of 0x1).

Fix-up the Linux device tree to update the PHY address for the second
Aquantia PHY on boards revisions D and up. Also rename the PHY node to
reflect the changes.

Signed-off-by: Camelia Groza &lt;camelia.groza@nxp.com&gt;
[Rebased]
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs
connected to MAC1 and MAC2. The second Aquantia PHY is located at a
different address on the MDIO bus compared to rev C (0x8 instead of 0x1).

Fix-up the Linux device tree to update the PHY address for the second
Aquantia PHY on boards revisions D and up. Also rename the PHY node to
reflect the changes.

Signed-off-by: Camelia Groza &lt;camelia.groza@nxp.com&gt;
[Rebased]
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>pg-wcom-ls102xa: fix sys counter frequency</title>
<updated>2021-06-17T06:16:11+00:00</updated>
<author>
<name>Aleksandar Gerasimovski</name>
<email>aleksandar.gerasimovski@hitachi-powergrids.com</email>
</author>
<published>2021-06-08T14:25:21+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=11eeeef7b02ad276c7593ef0f280dff477e8ba7b'/>
<id>11eeeef7b02ad276c7593ef0f280dff477e8ba7b</id>
<content type='text'>
A system clock of 66MHz was chosen for the pg-wcom-ls102xa.
Compared to the Evalboard, this corresponds to a reduction of 1/3.
The system counter clock should have been reduced accordingly,
but that was not the case, so we had a system time that was
1/3 behind the real time.

This patch corrects the system counter clock to
8.333MHz = 66.667MHz / 8.

Signed-off-by: Rainer Boschung &lt;rainer.boschung@hitachi-powergrids.com&gt;
Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A system clock of 66MHz was chosen for the pg-wcom-ls102xa.
Compared to the Evalboard, this corresponds to a reduction of 1/3.
The system counter clock should have been reduced accordingly,
but that was not the case, so we had a system time that was
1/3 behind the real time.

This patch corrects the system counter clock to
8.333MHz = 66.667MHz / 8.

Signed-off-by: Rainer Boschung &lt;rainer.boschung@hitachi-powergrids.com&gt;
Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>km: ls102x: update device disable configuration acc hw design desc</title>
<updated>2021-06-17T06:16:11+00:00</updated>
<author>
<name>Aleksandar Gerasimovski</name>
<email>aleksandar.gerasimovski@hitachi-powergrids.com</email>
</author>
<published>2021-06-08T14:23:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=ccbd2ced73d1ad310c34e75dca3ce30f1d515c85'/>
<id>ccbd2ced73d1ad310c34e75dca3ce30f1d515c85</id>
<content type='text'>
In order to improve power consumption ls102x allows to disable peripherals
that are not in use.
This patch follows SELI8 HW design description and disables peripherals
that are not in use in our designs, the same configuration is applicable
and for EXPU1.

This patch uses available hwconfig option for updating ls102x device
disable configuration.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In order to improve power consumption ls102x allows to disable peripherals
that are not in use.
This patch follows SELI8 HW design description and disables peripherals
that are not in use in our designs, the same configuration is applicable
and for EXPU1.

This patch uses available hwconfig option for updating ls102x device
disable configuration.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>km: ls102x: set ethrotate envvar to no</title>
<updated>2021-06-17T06:16:11+00:00</updated>
<author>
<name>Aleksandar Gerasimovski</name>
<email>aleksandar.gerasimovski@hitachi-powergrids.com</email>
</author>
<published>2021-06-08T14:21:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fd49502d0fe30ff5f7d63b572eb8871d013ebec6'/>
<id>fd49502d0fe30ff5f7d63b572eb8871d013ebec6</id>
<content type='text'>
The default behavior in the latest u-boot revisions is to rotate the
active net device to the next available if the requested link is not
established.

For our ls102x based devices this would mean that if active debug net
device is not available, u-boot will rotate and set the next net device
that is one of the estar adapters.
To return from this situation manual action to set correct ethact
adapter will be needed and this can be annoying when working in
debug mode.

Setting ethrotate=no will disable net adapter rotation and will make sure
that the primary adapter is always used.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The default behavior in the latest u-boot revisions is to rotate the
active net device to the next available if the requested link is not
established.

For our ls102x based devices this would mean that if active debug net
device is not available, u-boot will rotate and set the next net device
that is one of the estar adapters.
To return from this situation manual action to set correct ethact
adapter will be needed and this can be annoying when working in
debug mode.

Setting ethrotate=no will disable net adapter rotation and will make sure
that the primary adapter is always used.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>km: ls102xa: add missing define for PRAM regions</title>
<updated>2021-06-17T06:16:11+00:00</updated>
<author>
<name>Aleksandar Gerasimovski</name>
<email>aleksandar.gerasimovski@hitachi-powergrids.com</email>
</author>
<published>2021-06-08T14:19:08+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a09806498c2dcaf02a8f2fd41ab3bb595fc13ca4'/>
<id>a09806498c2dcaf02a8f2fd41ab3bb595fc13ca4</id>
<content type='text'>
In our designs we reserve PRAM area at the end of the RAM, and in order
this area to be visible and taken into account by the u-boot memory mgmt
CONFIG_PRAM has to be defined.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In our designs we reserve PRAM area at the end of the RAM, and in order
this area to be visible and taken into account by the u-boot memory mgmt
CONFIG_PRAM has to be defined.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>km/ls102xa: add support for u-boot POST memory test</title>
<updated>2021-06-17T06:16:11+00:00</updated>
<author>
<name>Aleksandar Gerasimovski</name>
<email>aleksandar.gerasimovski@hitachi-powergrids.com</email>
</author>
<published>2021-06-08T14:17:34+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3aea3ddf21a29145176189b55eca7a833b8f7a4d'/>
<id>3aea3ddf21a29145176189b55eca7a833b8f7a4d</id>
<content type='text'>
From production view this is standard test executed during production on
all linux based foxmc cards.
On CENT2 HW defined memory region is zero means that some DDR accesses are
done by memory_post_dataline and memory_post_addrline but pattern tests
are skipped that's why mem_regions is fast there.

On ls102x for the complete DDR region of 1GiB memory_regions_post_test
takes approx. 4min and this is too much for production, so this patch
defines only 1MiB region as compromise.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
From production view this is standard test executed during production on
all linux based foxmc cards.
On CENT2 HW defined memory region is zero means that some DDR accesses are
done by memory_post_dataline and memory_post_addrline but pattern tests
are skipped that's why mem_regions is fast there.

On ls102x for the complete DDR region of 1GiB memory_regions_post_test
takes approx. 4min and this is too much for production, so this patch
defines only 1MiB region as compromise.

Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>board/km: add support for expu1 design based on nxp</title>
<updated>2021-06-17T06:16:11+00:00</updated>
<author>
<name>Aleksandar Gerasimovski</name>
<email>aleksandar.gerasimovski@hitachi-powergrids.com</email>
</author>
<published>2021-06-08T14:16:28+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a7fd6fa1c277ed667d61de4e366fe034def4800a'/>
<id>a7fd6fa1c277ed667d61de4e366fe034def4800a</id>
<content type='text'>
The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.

The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.

Signed-off-by: Rainer Boschung &lt;rainer.boschung@hitachi-powergrids.com&gt;
Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
[Fixed new line error at EOF]
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.

The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.

Signed-off-by: Rainer Boschung &lt;rainer.boschung@hitachi-powergrids.com&gt;
Signed-off-by: Aleksandar Gerasimovski &lt;aleksandar.gerasimovski@hitachi-powergrids.com&gt;
[Fixed new line error at EOF]
Signed-off-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv8: layerscape: drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33</title>
<updated>2021-06-17T06:16:11+00:00</updated>
<author>
<name>Yangbo Lu</name>
<email>yangbo.lu@nxp.com</email>
</author>
<published>2021-06-03T02:51:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=34f39ce882d2ad214bc16341823ffba4476fde2a'/>
<id>34f39ce882d2ad214bc16341823ffba4476fde2a</id>
<content type='text'>
Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@nxp.com&gt;
Acked-by: Michael Walle &lt;michael@walle.cc&gt; [for kontron-sl28]
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Drop CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33. CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT
is used instead.

Signed-off-by: Yangbo Lu &lt;yangbo.lu@nxp.com&gt;
Acked-by: Michael Walle &lt;michael@walle.cc&gt; [for kontron-sl28]
Reviewed-by: Priyanka Jain &lt;priyanka.jain@nxp.com&gt;
</pre>
</div>
</content>
</entry>
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