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<title>u-boot.git/include/configs, branch v2021.10-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/include/configs?h=v2021.10-rc2</id>
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<updated>2021-08-12T13:33:39Z</updated>
<entry>
<title>Merge tag 'u-boot-rockchip-20210812' of https://source.denx.de/u-boot/custodians/u-boot-rockchip</title>
<updated>2021-08-12T13:33:39Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-08-12T13:33:39Z</published>
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<id>urn:sha1:07043055280a91d769ffe5e30d214241bd2e9e78</id>
<content type='text'>
- Add Rockchip SFC driver support;
- DTS sync from kernel;
- emmc hs400 support for rk3399;
- Fix for spinore bootdevice and MMC boot order;
</content>
</entry>
<entry>
<title>Merge https://source.denx.de/u-boot/custodians/u-boot-cfi-flash</title>
<updated>2021-08-11T12:31:56Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-08-11T12:31:56Z</published>
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<id>urn:sha1:a25277122dad99837b78cd3b3ae6b8214df88c26</id>
<content type='text'>
- Some CFI flash related fixups (Kconfig &amp; header) (Bin)
- Enable CFI flash support on the QEMU RISC-V virt machine. (Bin)
</content>
</entry>
<entry>
<title>Merge https://source.denx.de/u-boot/custodians/u-boot-marvell</title>
<updated>2021-08-11T12:31:25Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-08-11T12:31:25Z</published>
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<id>urn:sha1:4dc1a5c248ecbd06269a7854dd06c57e9a52f19c</id>
<content type='text'>
- Convert GoFlex Home Ethernet and SATA to Driver Model (Tony)
- mvebu: Automatically detect CONFIG_SYS_TCLK (Pavel)
- mvebu: sata_mv: Fix HDD identication during cold start (Tony)
- a37xx: pci: Fix handling PIO config error responses (Pavel)
- Other minor misc changes and board maintainer updates
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-amlogic-20210810' of https://source.denx.de/u-boot/custodians/u-boot-amlogic</title>
<updated>2021-08-11T12:31:13Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2021-08-11T12:31:13Z</published>
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<id>urn:sha1:aba3fa1d3f1dc8f7049317b8d6ea1d8cb8935e5e</id>
<content type='text'>
- odroid-n2: fix fdtfile suffix for n2-plus
- sei610 &amp; meson64_android cleanups to prepare android 11 boot support
- use Android BCB mechanism for reboot reason instead of HW reboot flag
- Switch meson64_android boot flow to use abootimg for A/B, AVB and DTBO support
</content>
</entry>
<entry>
<title>rockchip: Fix MMC boot order</title>
<updated>2021-08-11T09:44:01Z</updated>
<author>
<name>Alex Bee</name>
<email>knaerzche@gmail.com</email>
</author>
<published>2021-06-17T09:01:12Z</published>
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<id>urn:sha1:b212ad24a604b00b240add35516b7381965deb31</id>
<content type='text'>
Basically all, i.e. rk3036.dtsi, rk3128.dtsi, rk3xxx.dtsi, rk322x.dtsi,
rk3288.dtsi, rk3308-u-boot.dtsi, rk3328-u-boot.dtsi, rk3399-u-boot.dtsi
and px30-u-boot.dtsi Rockchip SoC devicetrees which have mmc indexes
are defining eMMC as mmc0 and sdmmc as mmc1.
This means that the rule to try to boot from the SD card first is ignored,
which as per comment is what we want and is important for distros, which
rely on that.

Fix this by setting the correct mmc index, i.e. first from mmc1 (SD card),
second from mmc0 (eMMC).

Signed-off-by: Alex Bee &lt;knaerzche@gmail.com&gt;
Reviewed-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>riscv: qemu: Enable MTD NOR flash support</title>
<updated>2021-08-11T08:36:10Z</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2021-08-07T05:00:02Z</published>
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<id>urn:sha1:d248627f9d4218688e7430bc714405a23885abfa</id>
<content type='text'>
Enable support to the 2 NOR flashes on the QEMU RISC-V virt machine.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: kirkwood: Do not overwrite CONFIG_SYS_TCLK</title>
<updated>2021-08-11T06:42:26Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2021-07-31T12:22:56Z</published>
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<id>urn:sha1:8ac303d49f891e11a5c0c4cce7a09a518cfb041b</id>
<content type='text'>
Config option CONFIG_SYS_TCLK is set by kw88f6281.h and kw88f6192.h files
to correct SOC/platform value. So do not overwrite it in board config
include files.

Kirkwood 88F6180 and 88F6192 uses 166 MHz TCLK and Kirkwood 88F6281 uses
200 MHz TCLK.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: mvebu: axp: Set CONFIG_SYS_TCLK globally</title>
<updated>2021-08-11T06:42:26Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2021-07-31T12:22:55Z</published>
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<id>urn:sha1:808cea90f5ab86fcdd9b0190fdb4c70cd6a060fc</id>
<content type='text'>
This mvebu axp platform always uses fixed 250 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.

Now every #if-#else case of soc.h file defines CONFIG_SYS_TCLK, so remove
useless default CONFIG_SYS_TCLK value from the end of soc.h file.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: mvebu: msys: Set CONFIG_SYS_TCLK globally</title>
<updated>2021-08-11T06:42:26Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2021-07-31T12:22:54Z</published>
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<id>urn:sha1:7dd26bbff8489da75ea2b80f0ebede03ee05de3c</id>
<content type='text'>
This mvebu msys platform always uses fixed 200 MHz TCLK. So specify this
CONFIG_SYS_TCLK option in msys section of global file soc.h file instead of
manual configuration in every board file.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR register</title>
<updated>2021-08-11T06:42:26Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2021-07-31T12:22:53Z</published>
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<id>urn:sha1:2ddf554b8648d892efc5733e7486cec5e93dc269</id>
<content type='text'>
Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz.
Use this information instead of manual configuration in every board file.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
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