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<title>u-boot.git/include/configs, branch v2023.01-rc1</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/include/configs?h=v2023.01-rc1</id>
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<updated>2022-11-07T06:46:28Z</updated>
<entry>
<title>arm: mvebu: Add RD-AC5X board</title>
<updated>2022-11-07T06:46:28Z</updated>
<author>
<name>Chris Packham</name>
<email>judge.packham@gmail.com</email>
</author>
<published>2022-11-05T04:24:00Z</published>
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<id>urn:sha1:6cc8b5db40b4d5fc23086a5116bdf1f0a3d3265a</id>
<content type='text'>
The RD-AC5X-32G16HVG6HLG-A0 development board main components and
features include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
  * SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
  * SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
  * PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
  * SR1: 88E2540*4
  * SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host
  port (shared with PCIe) Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
  connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~
  Port 48 (Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881
  solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)

Signed-off-by: Chris Packham &lt;judge.packham@gmail.com&gt;
</content>
</entry>
<entry>
<title>Makefile: Rename u-boot-spl.kwb to u-boot-with-spl.kwb</title>
<updated>2022-11-07T06:17:55Z</updated>
<author>
<name>Pali Rohár</name>
<email>pali@kernel.org</email>
</author>
<published>2022-11-02T17:51:28Z</published>
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<id>urn:sha1:87ac4b4b4ca5f00e2ddcdac41c9dc691ab2aecf1</id>
<content type='text'>
File name with pattern u-boot-spl* is used on all places except in kwb
image for binary with SPL-only code. Combined binary with both SPL and
proper U-Boot in other places has file name pattern u-boot-with-spl*.

Make it consistent also for kwb image and rename u-boot-spl.kwb to
u-boot-with-spl.kwb as this image contains both SPL and proper U-Boot code.

Also update documentation about file name changes.

Signed-off-by: Pali Rohár &lt;pali@kernel.org&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'mips-pull-2022-11-03' of https://source.denx.de/u-boot/custodians/u-boot-mips</title>
<updated>2022-11-04T00:23:27Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2022-11-04T00:23:27Z</published>
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<id>urn:sha1:45fc699cc54739c6f80ae4da920c121bc7d8665a</id>
<content type='text'>
- MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig
- MIPS: mtmips: fix incorrectly converted default value for CONFIG_SPL_PAD_TO
</content>
</entry>
<entry>
<title>MIPS: convert CONFIG_SYS_MIPS_TIMER_FREQ to Kconfig</title>
<updated>2022-11-02T20:42:32Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2022-07-10T15:15:14Z</published>
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<id>urn:sha1:a29491ade0adf3dbb9dc51be8b45530edde1f1df</id>
<content type='text'>
This converts the following to Kconfig:
    CONFIG_SYS_MIPS_TIMER_REQ

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>MIPS: mscc: remove unused CPU_CLOCK_RATE</title>
<updated>2022-11-02T20:42:32Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2022-07-10T15:15:13Z</published>
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<id>urn:sha1:ea24b0eacfffa7c3e7d25aa8e3d75d11fb13dca8</id>
<content type='text'>
CPU_CLOCK_RATE is just used once for CONFIG_SYS_MIPS_TIMER_FREQ
which is migrated to Kconfig in the next patch.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>MIPS: remove CONFIG_SYS_MHZ</title>
<updated>2022-11-02T20:42:32Z</updated>
<author>
<name>Daniel Schwierzeck</name>
<email>daniel.schwierzeck@gmail.com</email>
</author>
<published>2022-07-10T15:15:12Z</published>
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<id>urn:sha1:e9dcd5b40236b82672117464564d38511f1f7a0b</id>
<content type='text'>
Resolve all uses of CONFIG_SYS_MHZ with the currently defined value.
Remove code which depends on CONFIG_SYS_MHZ but where no board configs
actually use that code.

Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
</content>
</entry>
<entry>
<title>highbank: switch to use the Arm SP804 DM_TIMER driver</title>
<updated>2022-11-02T17:58:17Z</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2022-10-20T22:10:25Z</published>
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<id>urn:sha1:44b7abf8dc953f935d1de067cdace9dae2cbfb3c</id>
<content type='text'>
So far the Calxeda machines were using the CONFIG_SYS_TIMER_* macros to
simply hardcode the address of the counter register of the SP804 timer.
This method is deprecated and scheduled for removal.

Use the newly introduced SP804 DM_TIMER driver to provide timer
functionality on Highbank and Midway machines. The base address and base
frequency are taken from the devicetree.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
</entry>
<entry>
<title>stm32mp1: Add image information for capsule updates</title>
<updated>2022-10-31T18:47:32Z</updated>
<author>
<name>Sughosh Ganu</name>
<email>sughosh.ganu@linaro.org</email>
</author>
<published>2022-10-21T12:45:58Z</published>
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<id>urn:sha1:d70c4a0a20c3edba3375f51426da2aa7096f58df</id>
<content type='text'>
Enabling capsule update functionality on the platform requires
populating information on the images that are to be updated using the
functionality. Do so for the DK2 board.

Signed-off-by: Sughosh Ganu &lt;sughosh.ganu@linaro.org&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
Reviewed-by: Ilias Apalodimas &lt;ilias.apalodimas@linaro.org&gt;
Reviewed-by: Etienne Carriere &lt;etienne.carriere@linaro.org&gt;
</content>
</entry>
<entry>
<title>Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE</title>
<updated>2022-10-31T15:01:31Z</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2022-10-21T00:22:39Z</published>
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<id>urn:sha1:984639039f4cfe32ec2cc531d6ace05326ac49eb</id>
<content type='text'>
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>arm: bcmbca: remove bcm6753 support under CONFIG_ARCH_BCM6753</title>
<updated>2022-10-31T12:55:59Z</updated>
<author>
<name>William Zhang</name>
<email>william.zhang@broadcom.com</email>
</author>
<published>2022-08-22T18:49:07Z</published>
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<id>urn:sha1:779a7b665f59b63ba55b596138db188de2810d09</id>
<content type='text'>
BCM6753 is essentially same as the main chip BCM6855 but with different
SKU number. Now that BCM6855 is supported under CONFIG_ARCH_BCMBCA and
CONFIG_BCM6855, remove the original ARCH_BCM6753 support and migrate its
configuration and dts settings. This includes:
- Remove the bcm96753ref board folder. It is replaced by the
generic bcmbca board folder.
- Merge the 6753.dtsi setting to the new 6855.dtsi file. Update
96753ref board dts with the new compatible string.
- Delete broadcom_bcm96763ref.h and merge its setting to the new
bcm96855.h file.
- Delete bcm96753ref_ram_defconfig and use a basic config version of
bcm96855_defconfig

Signed-off-by: William Zhang &lt;william.zhang@broadcom.com&gt;
Reviewed-by: Philippe Reynes &lt;philippe.reynes@softathome.com&gt;
</content>
</entry>
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