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<title>u-boot.git/include/configs, branch v2025.10-rc2</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/include/configs?h=v2025.10-rc2</id>
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<updated>2025-08-08T14:20:52Z</updated>
<entry>
<title>include: configs: Add config header file for Agilex7 M-series</title>
<updated>2025-08-08T14:20:52Z</updated>
<author>
<name>Tingting Meng</name>
<email>tingting.meng@altera.com</email>
</author>
<published>2025-08-04T01:24:52Z</published>
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<id>urn:sha1:f64130138aa743e1508f275c56593b85168b53a2</id>
<content type='text'>
Add config header file for new platform Agilex7 M-series.

Signed-off-by: Tingting Meng &lt;tingting.meng@altera.com&gt;
Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: soc64: Perform warm reset after L2 reset in SPL</title>
<updated>2025-08-08T14:20:50Z</updated>
<author>
<name>Alif Zakuan Yuslaimi</name>
<email>alif.zakuan.yuslaimi@altera.com</email>
</author>
<published>2025-08-04T01:24:45Z</published>
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<id>urn:sha1:71916a72f106ed2aaae5a49885fb86623e5f7aec</id>
<content type='text'>
SPL checks for a magic word in the system manager's scratch
register to determine if an L2 reset has occurred. If detected,
SPL places all slave CPUs (CPU1–3) into WFI mode. The master
CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3
system register and also enters WFI mode.

This warm reset flow is handled entirely within the HPS. The
function `socfpga_sysreset_request()` triggers the warm
reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S`
handles the necessary initialization.

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
</entry>
<entry>
<title>sysreset: socfpga: soc64: Enable L2 reset</title>
<updated>2025-08-08T14:20:50Z</updated>
<author>
<name>Alif Zakuan Yuslaimi</name>
<email>alif.zakuan.yuslaimi@altera.com</email>
</author>
<published>2025-08-04T01:24:44Z</published>
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<id>urn:sha1:c8f5166cff0ccdb1966ed786dba88e9548ce632e</id>
<content type='text'>
Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes
the magic word into system manager's scratch register to indicate
the system has performed L2 reset and request reset manager to
perform hardware handshake and then trigger L2 reset. CPU0 put
itself into WFI mode. L2 reset will reboot all HPS CPU cores after
which all HPS cores are in WFI mode. L2 reset is followed by warm
reset request by SPL via RMR_EL3 system register.

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
</entry>
<entry>
<title>include: configs: socfpga: Add environment variables for distro boot</title>
<updated>2025-08-08T14:20:49Z</updated>
<author>
<name>Alif Zakuan Yuslaimi</name>
<email>alif.zakuan.yuslaimi@altera.com</email>
</author>
<published>2025-08-04T01:24:42Z</published>
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<id>urn:sha1:9a7881abeb8c57e6d132c9303e487409a5340e51</id>
<content type='text'>
Added environment variables needed to support NAND distro boot

Signed-off-by: Alif Zakuan Yuslaimi &lt;alif.zakuan.yuslaimi@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
</entry>
<entry>
<title>arm: bcm281xx: Remove ethernet driver</title>
<updated>2025-08-01T07:30:47Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-07-18T01:15:44Z</published>
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<id>urn:sha1:3c1ac44caaa243acb7c3fe0aca412778b8cc28e6</id>
<content type='text'>
As no platforms enable the ethernet driver, remove it.

Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-stm32-20250731' of https://source.denx.de/u-boot/custodians/u-boot-stm</title>
<updated>2025-07-31T16:04:32Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-07-31T14:45:50Z</published>
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<id>urn:sha1:f5e968a28e7cdc2c4365f5a382e02f074ee03fac</id>
<content type='text'>
CI: https://source.denx.de/u-boot/custodians/u-boot-stm/-/pipelines/27236

- Add support for STM32 TIMERS and STM32 PWM on STM32MP25
- Add STM32MP13xx SPL and OpTee-OS start support
- Fix header misuse in stm32 reset drivers
- Fix STMicroelectronics spelling
- Fix clk-stm32h7 wrong macros used in register read
- Fix PRE_CON_BUF_ADDR on STM32MP13
- Fix clock identifier passed to struct scmi_clk_parent_set_in
- Fix stm32 reset for STM32F4/F7 and H7
- Enable OF_UPSTREAM_BUILD_VENDOR for stm32mp13_defconfig
- Add STM32MP23 SoC and stm32mp235f-dk board support
</content>
</entry>
<entry>
<title>configs: socfpga: soc64: agilex5: Enable NAND boot with UBI / UBIFS</title>
<updated>2025-07-30T09:45:31Z</updated>
<author>
<name>Dinesh Maniyam</name>
<email>dinesh.maniyam@altera.com</email>
</author>
<published>2025-07-04T06:09:56Z</published>
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<id>urn:sha1:169039f4f1df82cd4aeb95a9480b2bf5350c975c</id>
<content type='text'>
Add the required configuration in the U-Boot env to enable Linux NAND
boot with UBI / UBIFS.

Signed-off-by: Dinesh Maniyam &lt;dinesh.maniyam@altera.com&gt;
Reviewed-by: Tien Fong Chee &lt;tien.fong.chee@altera.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'u-boot-marvell-20250729' of https://source.denx.de/u-boot/custodians/u-boot-marvell</title>
<updated>2025-07-29T15:36:59Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2025-07-29T15:36:59Z</published>
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<id>urn:sha1:808d4bc2bdcedb9ffca57b85984e53d39e1cb718</id>
<content type='text'>
CI: https://dev.azure.com/sr0718/u-boot/_build/results?buildId=394&amp;view=results

- cmd: tlv_eeprom: Minor improvements (Hugo)
- kirkwood: Enable bootstd and other modernization for ib62x0 board
  (Tony)
- spi: mvebu: Correct dependencies on MVEBU_A3700_SPI (Tom)
- ddr: marvell: a38x: Fix unsigned issues detected by smatch (Andrew)
</content>
</entry>
<entry>
<title>treewide: Fix STMicroelectronics spelling</title>
<updated>2025-07-29T15:02:32Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2025-07-28T13:08:31Z</published>
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<id>urn:sha1:1cec03bb1f8baee0bda151392ea1b5bb7c742547</id>
<content type='text'>
Fix STMicroelectronics spelling in comments.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
<entry>
<title>ARM: stm32mp: Add STM32MP23 support</title>
<updated>2025-07-29T15:02:31Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2025-06-26T08:08:45Z</published>
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<id>urn:sha1:fdd30ee308a29e3dcfbadb1587c2ad01c45e6530</id>
<content type='text'>
Add STM32MP23 support which is a cost optimized of STM32MP25.
More details available at:
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
</content>
</entry>
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