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<title>u-boot.git/include/configs, branch v2026.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>ARM: stm32mp: Add STM32MP21 support</title>
<updated>2026-02-24T16:41:48+00:00</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2026-02-03T16:49:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=d557099fb0f1b1b8ae0a415e006c3d517874b8a6'/>
<id>d557099fb0f1b1b8ae0a415e006c3d517874b8a6</id>
<content type='text'>
STM32MP21 application processors (STM32 MPUs) based on a single
Arm Cortex®-A35 core running up to 1.5 GHz and Cortex®-M33 core
running at 300 MHz.

It is pin-compatible with the STM32MP2 series in the VFBGA361
10×10 mm package: the STM32MP21 uses a subset of the STM32MP23
pinout, which itself is a subset of the STM32MP25.

More details available here :
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
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<pre>
STM32MP21 application processors (STM32 MPUs) based on a single
Arm Cortex®-A35 core running up to 1.5 GHz and Cortex®-M33 core
running at 300 MHz.

It is pin-compatible with the STM32MP2 series in the VFBGA361
10×10 mm package: the STM32MP21 uses a subset of the STM32MP23
pinout, which itself is a subset of the STM32MP25.

More details available here :
https://www.st.com/en/microcontrollers-microprocessors/stm32mp2-series.html

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm64: versal2: fix GICD/GICR base addresses for Versal Gen 2</title>
<updated>2026-02-11T08:26:17+00:00</updated>
<author>
<name>Maheedhar Bollapalli</name>
<email>maheedharsai.bollapalli@amd.com</email>
</author>
<published>2026-02-10T11:02:06+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=85bbd16750ed7a4907666bfa01effc39ef1f4c0c'/>
<id>85bbd16750ed7a4907666bfa01effc39ef1f4c0c</id>
<content type='text'>
Versal2 was using wrong GIC base mappings, causing GICR_TYPER reads to
not match EL1 MPIDR. This led U-Boot to walk beyond the per-CPU GICR
frames, access out-of-range addresses, and hit a synchronous exception
during early gic init percpu while booting up on alternate core
i.e., non cpu0.

Update Versal Gen 2 headers to the correct Versal Gen 2 bases.

Signed-off-by: Maheedhar Bollapalli &lt;maheedharsai.bollapalli@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/d0bc3fe1af8409fcfe505e55fb7042a33b845a4e.1770721325.git.michal.simek@amd.com
</content>
<content type='xhtml'>
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<pre>
Versal2 was using wrong GIC base mappings, causing GICR_TYPER reads to
not match EL1 MPIDR. This led U-Boot to walk beyond the per-CPU GICR
frames, access out-of-range addresses, and hit a synchronous exception
during early gic init percpu while booting up on alternate core
i.e., non cpu0.

Update Versal Gen 2 headers to the correct Versal Gen 2 bases.

Signed-off-by: Maheedhar Bollapalli &lt;maheedharsai.bollapalli@amd.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@amd.com&gt;
Link: https://lore.kernel.org/r/d0bc3fe1af8409fcfe505e55fb7042a33b845a4e.1770721325.git.michal.simek@amd.com
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge patch series "m68k: Add support for QEMU virt machine"</title>
<updated>2026-02-02T20:25:48+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-02-02T20:24:56+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=1de103fc29761fa729dffaa15d0cfb2766be05e4'/>
<id>1de103fc29761fa729dffaa15d0cfb2766be05e4</id>
<content type='text'>
Kuan-Wei Chiu &lt;visitorckw@gmail.com&gt; says:

Add support for the QEMU 'virt' machine on the m68k architecture. The
QEMU virt machine models a generic system utilizing Goldfish virtual
peripherals and is capable of emulating various classic 68k CPUs.

Currently, U-Boot's m68k architecture support focuses on ColdFire
variants. This series expands support to include the classic M680x0
architecture, implementing the necessary exception vectors, startup
code, and a bootinfo parser compatible with the QEMU interface.

Drivers for Goldfish peripherals (TTY, Timer, RTC) and the QEMU
Virtual System Controller (sysreset) are also added to enable serial
console, timekeeping, and system reset functionality.

The implementation has been verified on QEMU targeting the M68040 CPU,
confirming successful hardware initialization and boot to the U-Boot
command shell. Additionally, the CI configuration was verified locally
using gitlab-ci-local "qemu_m68k_virt test.py", resulting in
PASS qemu_m68k_virt test.py.

Link: https://lore.kernel.org/r/20260107201838.3448806-1-visitorckw@gmail.com
[trini: Re-sort MAINTAINERS entries]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Kuan-Wei Chiu &lt;visitorckw@gmail.com&gt; says:

Add support for the QEMU 'virt' machine on the m68k architecture. The
QEMU virt machine models a generic system utilizing Goldfish virtual
peripherals and is capable of emulating various classic 68k CPUs.

Currently, U-Boot's m68k architecture support focuses on ColdFire
variants. This series expands support to include the classic M680x0
architecture, implementing the necessary exception vectors, startup
code, and a bootinfo parser compatible with the QEMU interface.

Drivers for Goldfish peripherals (TTY, Timer, RTC) and the QEMU
Virtual System Controller (sysreset) are also added to enable serial
console, timekeeping, and system reset functionality.

The implementation has been verified on QEMU targeting the M68040 CPU,
confirming successful hardware initialization and boot to the U-Boot
command shell. Additionally, the CI configuration was verified locally
using gitlab-ci-local "qemu_m68k_virt test.py", resulting in
PASS qemu_m68k_virt test.py.

Link: https://lore.kernel.org/r/20260107201838.3448806-1-visitorckw@gmail.com
[trini: Re-sort MAINTAINERS entries]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>board: Add QEMU m68k virt board support</title>
<updated>2026-02-02T20:24:41+00:00</updated>
<author>
<name>Kuan-Wei Chiu</name>
<email>visitorckw@gmail.com</email>
</author>
<published>2026-01-07T20:18:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=516afc8f76268fceb98f6b891a653484e931b26a'/>
<id>516afc8f76268fceb98f6b891a653484e931b26a</id>
<content type='text'>
Add support for the QEMU 'virt' machine on the m68k architecture. This
board emulates a generic machine based on the Motorola 68040 CPU
equipped with Goldfish virtual peripherals.

Introduce the necessary board configuration and initialization
infrastructure. The implementation includes logic to parse the QEMU
bootinfo interface, enabling dynamic detection of system RAM size to
adapt to the virtual machine's configuration.

Enable the Goldfish TTY driver for serial console output. Additionally,
enable Goldfish RTC and timer drivers to support real-time clock
functionality and nanosecond-resolution delays. Include comprehensive
documentation covering build instructions and usage examples.

Signed-off-by: Kuan-Wei Chiu &lt;visitorckw@gmail.com&gt;
Tested-by: Daniel Palmer &lt;daniel@0x0f.com&gt;
Reviewed-by: Simon Glass &lt;simon.glass@canonical.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for the QEMU 'virt' machine on the m68k architecture. This
board emulates a generic machine based on the Motorola 68040 CPU
equipped with Goldfish virtual peripherals.

Introduce the necessary board configuration and initialization
infrastructure. The implementation includes logic to parse the QEMU
bootinfo interface, enabling dynamic detection of system RAM size to
adapt to the virtual machine's configuration.

Enable the Goldfish TTY driver for serial console output. Additionally,
enable Goldfish RTC and timer drivers to support real-time clock
functionality and nanosecond-resolution delays. Include comprehensive
documentation covering build instructions and usage examples.

Signed-off-by: Kuan-Wei Chiu &lt;visitorckw@gmail.com&gt;
Tested-by: Daniel Palmer &lt;daniel@0x0f.com&gt;
Reviewed-by: Simon Glass &lt;simon.glass@canonical.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge patch series "arm: mach-k3: j721s2: Provide a way to obtain boot device for non SPLs"</title>
<updated>2026-02-02T19:39:52+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-02-02T19:39:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=4b287e0a3ae4ab3159584cb5ae12c9b470716be8'/>
<id>4b287e0a3ae4ab3159584cb5ae12c9b470716be8</id>
<content type='text'>
This series from Dominik Haller &lt;d.haller@phytec.de&gt; provides a way for
TI K3 platforms to determine their boot device outside of SPL and then
adds support for the PHYTEC phyCORE-AM68x/TDA4x SoM.

Link: https://lore.kernel.org/r/20260116014116.767555-1-d.haller@phytec.de
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This series from Dominik Haller &lt;d.haller@phytec.de&gt; provides a way for
TI K3 platforms to determine their boot device outside of SPL and then
adds support for the PHYTEC phyCORE-AM68x/TDA4x SoM.

Link: https://lore.kernel.org/r/20260116014116.767555-1-d.haller@phytec.de
</pre>
</div>
</content>
</entry>
<entry>
<title>board: phytec: Add PHYTEC phyCORE-AM68x/TDA4x SoM</title>
<updated>2026-02-02T19:39:42+00:00</updated>
<author>
<name>Dominik Haller</name>
<email>d.haller@phytec.de</email>
</author>
<published>2026-01-16T01:41:12+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e9fa9a2fe325e7030f01f3bd62bf4d571ec6a6c1'/>
<id>e9fa9a2fe325e7030f01f3bd62bf4d571ec6a6c1</id>
<content type='text'>
Add support for the PHYTEC phyCORE-AM68x/TDA4x (J721S2 family) SoM.

Supported features:
- 4GB LPDDR4 RAM
- eMMC
- SD-Card
- Ethernet
- OSPI
- AVS
- debug UART

Signed-off-by: Dominik Haller &lt;d.haller@phytec.de&gt;
Reviewed-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for the PHYTEC phyCORE-AM68x/TDA4x (J721S2 family) SoM.

Supported features:
- 4GB LPDDR4 RAM
- eMMC
- SD-Card
- Ethernet
- OSPI
- AVS
- debug UART

Signed-off-by: Dominik Haller &lt;d.haller@phytec.de&gt;
Reviewed-by: Wadim Egorov &lt;w.egorov@phytec.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>armv7: Add CPLD support via IFC to the ls1021a-iot board.</title>
<updated>2026-01-28T06:26:50+00:00</updated>
<author>
<name>Mateus Lima Alves</name>
<email>mateuslima.ti@gmail.com</email>
</author>
<published>2026-01-26T16:05:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=424b324165ea0343598c5a8b52591ea504dcde52'/>
<id>424b324165ea0343598c5a8b52591ea504dcde52</id>
<content type='text'>
This patch adds CPLD support via IFC to the ls1021a-iot board.

Signed-off-by: Mateus Lima Alves &lt;mateuslima.ti@gmail.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This patch adds CPLD support via IFC to the ls1021a-iot board.

Signed-off-by: Mateus Lima Alves &lt;mateuslima.ti@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>arm: Remove remainder of ARCH_ORION5X</title>
<updated>2026-01-21T18:05:15+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-01-15T21:27:22+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b9d4a17b90fd3b98023da5cf3b45a1a5058fb0ad'/>
<id>b9d4a17b90fd3b98023da5cf3b45a1a5058fb0ad</id>
<content type='text'>
With commit 5663b137e682 ("arm: Remove edminiv2 board") the last
ARCH_ORION5X platform was removed. Remove the rest of the architecture
code which is now unused.

Reviewed-by: Tony Dinh &lt;mibodhi@gmail.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
With commit 5663b137e682 ("arm: Remove edminiv2 board") the last
ARCH_ORION5X platform was removed. Remove the rest of the architecture
code which is now unused.

Reviewed-by: Tony Dinh &lt;mibodhi@gmail.com&gt;
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'xilinx-for-v2026.04-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze</title>
<updated>2026-01-19T19:08:48+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2026-01-19T19:08:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=55ca2110d74f8e5a594aecc11ce4103dc73e9e02'/>
<id>55ca2110d74f8e5a594aecc11ce4103dc73e9e02</id>
<content type='text'>
AMD/Xilinx/FPGA changes for v2026.04-rc1 v2

microblaze:
- Fix spl_boot_list order

versal2:
- Fix EMMC distro boot setup
- Align distro boot variables with memory layout

zynqmp-phy:
- Sync with Linux kernel driver

zynqmp:
- Add verify_auth command
- DT sync
- Add placing variables to FAT/EXT4
- Enable PCIe driver by default

pcie - xilinx-nwl:
- Fix Link down crash

ufs:
- Align clock/reset with DT binding

# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYIAB0WIQSXAixArPbWpRanWW+rB/7wTvUR9QUCaW3p3wAKCRCrB/7wTvUR
# 9VkwAP4jPRALpM34VpTimNe/iwigIx8hAHxbvkUU0oJ/DW6W8AEAhCSL+ydgreuv
# kKCyNiOF1sm8IrOh4TdtMIFn37d4Dwg=
# =AkKK
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 19 Jan 2026 02:22:55 AM CST
# gpg:                using EDDSA key 97022C40ACF6D6A516A7596FAB07FEF04EF511F5
# gpg: Can't check signature: No public key
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
AMD/Xilinx/FPGA changes for v2026.04-rc1 v2

microblaze:
- Fix spl_boot_list order

versal2:
- Fix EMMC distro boot setup
- Align distro boot variables with memory layout

zynqmp-phy:
- Sync with Linux kernel driver

zynqmp:
- Add verify_auth command
- DT sync
- Add placing variables to FAT/EXT4
- Enable PCIe driver by default

pcie - xilinx-nwl:
- Fix Link down crash

ufs:
- Align clock/reset with DT binding

# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYIAB0WIQSXAixArPbWpRanWW+rB/7wTvUR9QUCaW3p3wAKCRCrB/7wTvUR
# 9VkwAP4jPRALpM34VpTimNe/iwigIx8hAHxbvkUU0oJ/DW6W8AEAhCSL+ydgreuv
# kKCyNiOF1sm8IrOh4TdtMIFn37d4Dwg=
# =AkKK
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 19 Jan 2026 02:22:55 AM CST
# gpg:                using EDDSA key 97022C40ACF6D6A516A7596FAB07FEF04EF511F5
# gpg: Can't check signature: No public key
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: imx: Enable boot from both USB controllers on all i.MX6 DHSOM</title>
<updated>2026-01-17T18:00:42+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marex@nabladev.com</email>
</author>
<published>2026-01-10T20:34:19+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9a030f4c5151056f16f6c2300de7a0ad6f2a812e'/>
<id>9a030f4c5151056f16f6c2300de7a0ad6f2a812e</id>
<content type='text'>
Enable boot from both USB controller 0 and 1 on all i.MX6 DHSOM.

Signed-off-by: Marek Vasut &lt;marex@nabladev.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Enable boot from both USB controller 0 and 1 on all i.MX6 DHSOM.

Signed-off-by: Marek Vasut &lt;marex@nabladev.com&gt;
</pre>
</div>
</content>
</entry>
</feed>
