u-boot.git/include/configs, branch v2026.07

arm: mediatek: mt7988: fix gd->bd->bi_dram[0].size

2026-06-24T15:06:16Z

Use board_get_usable_ram_top() instead of get_effective_memsize() to set gd->ram_top to something <= 4GiB. Both board_get_usable_ram_top() and get_effective_memsize() are used to set gd->ram_top in setup_dest_addr(). However, get_effective_memsize() also sets gd->bd->bi_dram[0].size in dram_init_banksize(), which is undesirable. Prior to commit bddd6bbef3dc ("arm: mediatek: mt7988: drop dram_init_banksize()"), gd->bd->bi_dram[0].size was overridden in a board-specific dram_init_banksize() implementation. When that was removed get_effective_memsize() set gd->bd->bi_dram[0].size to the wrong value because of CFG_MAX_MEM_MAPPED. Rather than continue to use an old-style CFG_ option and the potentially confusing overriding of gd->bd->bi_dram[0].size (it is difficult to see which order the functions that set it are called), we can just use board_get_usable_ram_top() to set gd->ram_top to the correct value instead. This is possible now, thanks to LMB_LIMIT_DMA_BELOW_RAM_TOP being set by default for 64-bit Mediatek ARM SoCs. The CFG_MAX_MEM_MAPPED option is removed since it is no longer needed. The config header and Kconfig option are also removed since that was the last CFG_ option. Reported-by: Rudy Andram Closes: https://lore.kernel.org/u-boot/20260602162233.2418471-1-rmandrad@gmail.com/ Fixes: bddd6bbef3dc ("arm: mediatek: mt7988: drop dram_init_banksize()") Link: https://patch.msgid.link/20260615-mtk-fix-ram-size-v2-4-f72cfc52ce58@baylibre.com Signed-off-by: David Lechner

arm: mediatek: mt7987: fix gd->bd->bi_dram[0].size

2026-06-24T15:06:16Z

Use board_get_usable_ram_top() instead of get_effective_memsize() to set gd->ram_top to something <= 4GiB. Both board_get_usable_ram_top() and get_effective_memsize() are used to set gd->ram_top in setup_dest_addr(). However, get_effective_memsize() also sets gd->bd->bi_dram[0].size in dram_init_banksize(), which is undesirable. Prior to commit 56183fb025c2 ("arm: mediatek: mt7987: drop dram_init_banksize()"), gd->bd->bi_dram[0].size was overridden in a board-specific dram_init_banksize() implementation. When that was removed get_effective_memsize() set gd->bd->bi_dram[0].size to the wrong value because of CFG_MAX_MEM_MAPPED. Rather than continue to use an old-style CFG_ option and the potentially confusing overriding of gd->bd->bi_dram[0].size (it is difficult to see which order the functions that set it are called), we can just use board_get_usable_ram_top() to set gd->ram_top to the correct value instead. This is possible now, thanks to LMB_LIMIT_DMA_BELOW_RAM_TOP being set by default for 64-bit Mediatek ARM SoCs. On mt7987, there is already an implementation of board_get_usable_ram_top() for other reasons, so it is modified to also limit ram_top to 4GiB (mt7987 is currently the only thing that sets CONFIG_MTK_TZ_MOVABLE=y so it is safe to change this here without unintentional side-effects). The CFG_MAX_MEM_MAPPED option is removed since it is no longer needed. The config header and Kconfig option are also removed since that was the last CFG_ option. Fixes: 56183fb025c2 ("arm: mediatek: mt7987: drop dram_init_banksize()") Link: https://patch.msgid.link/20260615-mtk-fix-ram-size-v2-3-f72cfc52ce58@baylibre.com Signed-off-by: David Lechner

arm: dts: renesas: Enable DBSC5 on R-Car R8A78000 X5H Cortex-M33 RSIP port

2026-06-16T03:38:25Z

Bind the DBSC5 DRAM controller driver on boot in board_early_init_r(), which brings up the DBSC5 DRAM controller and its PHY and which enables access to DRAM present on this system. Add default boot command which loads additional bootloader components from HF and UFS storage into SRAM and DRAM, and starts those components on SCP and AP core 0. The system is then capable of reaching U-Boot on the AP core 0. Specifically, the following components are loaded: - SCP firmware, 384 kiB from HF offset 0x4c0000 to SCP STCM - TFA BL31, 256 kiB from UFS0 offset 0x5000 * 4 kiB sectors to DRAM 0x8c200000 - TEE, 2 MiB from UFS0 offset 0x5200 * 4 kiB sectors to DRAM 0x8c400000 - U-Boot, 1 MiB from UFS0 offset 0x7200 * 4 kiB sectors to DRAM 0x8c300000 - IPL parameters table is generated at DRAM address 0x8c100000 Enable pstore command support to allow dumping kernel console from pstore/ramoops, which is convenient for debugging. Use as follows: => pstore set 0x80000000 0x10000 0x400 0x8000 0 0 0 => pstore display console Signed-off-by: Marek Vasut

arm64: dts: renesas: r8a779md: Add support for R-Car M3Le R8A779MD Geist

2026-05-31T22:02:30Z

Add support for the Geist board based on the Renesas R8A779MD (M3Le) SoC, a register-compatible variant of the R8A77965 (M3N) with reduced peripherals. The Geist board design references the Renesas Salvator-X/XS boards, adapting their configuration for the R8A779MD SoC. The board will be switched to OF_UPSTREAM once the DTs land in upstream. Signed-off-by: Huy Bui Signed-off-by: Nguyen Tran Signed-off-by: Marek Vasut

board: st: stm32mp15: support dynamic A/B bank bootup

2026-05-26T11:46:30Z

Following commit 4300f9f4c5d7 ("board: st: stm32mp25: support dynamic A/B bank bootup"), this patch enables automatic detection of the active A/B bank on STM32MP15 platforms by retrieving partition GUIDs from FWU metadata. This ensures the system correctly identifies the bootable partitions even in multi-bank scenarios, falling back to a standard bootable flag scan if the UUIDs are missing. To enable A/B bank bootup on STM32MP15 boards, add the following Kconfig options to the stm32mp15[_basic]_defconfig: CONFIG_FWU_MULTI_BANK_UPDATE=y CONFIG_FWU_MDATA=y CONFIG_FWU_NUM_BANKS=2 CONFIG_FWU_NUM_IMAGES_PER_BANK=3 CONFIG_CMD_FWU_METADATA=y CONFIG_FWU_MDATA_V2=y Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard

arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port

2026-05-21T19:48:05Z

Add support for building U-Boot for Cortex-M33 RSIP core in Renesas R-Car Gen5 R8A78000 X5H SoC. The main goal is to start U-Boot on the Cortex-M33 RSIP core, which initializes the hardware and then starts the Cortex-M33 SCP and Cortex-A720 cores which run the SCP firmware and applications software respectively. The SCP is responsible for platform resource management, and is used to start other CPU cores. The Cortex-M33 build contains its own r8a78000_ironhide_cm33_defconfig which configures the build for aarch32 instruction set compatible with the ARMv8M core. The build also uses -cm33 DT and -u-boot.dtsi which are derived from their non-CM33 counterparts, and add CM33 specifics. The arch/arm/mach-renesas/u-boot-rsip.lds is derived from generic arch/arm/cpu/u-boot.lds with adjustments to cater to the RSIP core, those are entrypoint before vectors, __data_start/__data_end symbols for data-only relocation, and placement of BSS into read-write SRAM area. Signed-off-by: Marek Vasut

arm64: renesas: Select HSCIF for DEBUG UART on R-Car Gen5 R8A78000 X5H

2026-05-21T19:48:05Z

The R-Car Gen5 R8A78000 X5H uses HSCIF as default serial console interface. Select CFG_HSCIF to make debug UART code also configure serial console interface as HSCIF instead of SCIF in case the CONFIG_DEBUG_UART would be enabled. Signed-off-by: Marek Vasut

arm64: dts: renesas: Switch to upstream DT on Renesas R-Car X5H R8A78000

2026-05-21T19:48:05Z

Enable OF_UPSTREAM to use upstream Linux kernel DT source as a base for U-Boot control DT. Retain currently present parts of the DT which are not yet part of upstream Linux kernel DT in -u-boot.dtsi files until they get replaced by upstream equivalents. Add renesas/ prefix to the DEFAULT_DEVICE_TREE as part of the switch. Unused i2c2..i2c8 nodes have been removed, and will become available once upstream Linux kernel DT adds those nodes. The DRAM_RSV_SIZE has been updated to cover first 518 MiB of DRAM, which are reserved for firmware and other use. Note that all DT parts in -u-boot.dtsi are not considered stable DT bindings and may change before they land in Linux kernel and become stable DT ABI. Signed-off-by: Marek Vasut

board: nxp: lx2160a: without QIXIS, MC-ENET, PCI, LTC3882

2026-05-15T11:28:31Z

The shared LX2160A board file calls helpers that only exist when their subsystem is enabled. Gate them on the matching CONFIG_*: - pci_init() under CONFIG_PCI. - fdt_fixup_mc_ddr() and fsl_rgmii_init() under CONFIG_FSL_MC_ENET. - qixis_*() and the QIXIS branch of checkboard() under CONFIG_FSL_QIXIS; cpu_name(buf) moves out so the non-QIXIS path still prints "Board: ". - EVENT_SPY_SIMPLE on init_func_vid moves inside the CONFIG_VOL_MONITOR_LTC3882_READ guard (was outside, dangling symbol when LTC3882 off). #if / #ifdef, not IS_ENABLED(), because the helpers are themselves conditionally compiled. While here, lx2160a_common.h: fix BOOT_TARGET_DEVICES_MMC 1 arg vs 2 args and gate the MMC target on CONFIG_CMD_MMC, not CONFIG_MMC. No functional change for NXP boards: LX2160ARDB, LX2160AQDS, or LX2162AQDS, but mainly build clean up in order to support other NXP lx2160a boards without those HW dependencies. Signed-off-by: Vincent Jardin Signed-off-by: Peng Fan

p2041rdb: use the upstream device tree

2026-05-15T11:28:30Z

Switch to the upstream device tree, which already includes the UART nodes we need for the DM. We also need to increase malloc area before relocation otherwise you'll get the following error and the board panics: DRAM: Initializing....using SPD alloc space exhausted ptr 414 limit 400 Signed-off-by: Michael Walle Signed-off-by: Peng Fan