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<title>u-boot.git/include/dt-bindings/clock, branch v2016.03</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>tegra: dts: Sync up the tegra124 device tree files with Linux</title>
<updated>2016-02-16T16:17:50+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-01-30T23:37:43+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f4abbee3ae8f64871ba91bcf1ef7f5b5387fbb1f'/>
<id>f4abbee3ae8f64871ba91bcf1ef7f5b5387fbb1f</id>
<content type='text'>
Sync up these files with Linux v4.4.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
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<pre>
Sync up these files with Linux v4.4.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.</title>
<updated>2016-02-01T21:14:00+00:00</updated>
<author>
<name>Purna Chandra Mandal</name>
<email>purna.mandal@microchip.com</email>
</author>
<published>2016-01-28T10:00:11+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a0e7908326b9dcde4c27dbbcbc52ccbf9e009255'/>
<id>a0e7908326b9dcde4c27dbbcbc52ccbf9e009255</id>
<content type='text'>
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
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<pre>
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal &lt;purna.mandal@microchip.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: Bring in RK3036 device tree file includes and bindings</title>
<updated>2015-12-01T15:07:22+00:00</updated>
<author>
<name>huang lin</name>
<email>hl@rock-chips.com</email>
</author>
<published>2015-11-17T06:20:15+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=fc0fada0943133940e6052879df91ab0e2c8cf16'/>
<id>fc0fada0943133940e6052879df91ab0e2c8cf16</id>
<content type='text'>
Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases
we need in uboot

Signed-off-by: Lin Huang &lt;hl@rock-chips.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Since rk3036 device tree file still in reviewing, bring it from
https://patchwork.kernel.org/patch/7203371/ and add some aliases
we need in uboot

Signed-off-by: Lin Huang &lt;hl@rock-chips.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rockchip: Bring in RK3288 device tree file includes and bindings</title>
<updated>2015-09-03T03:28:23+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-08-30T22:55:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=344c837686b4268882ee4942f2a1e5e5716c7383'/>
<id>344c837686b4268882ee4942f2a1e5e5716c7383</id>
<content type='text'>
Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
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<pre>
Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: Tegra210: Add SoC code/include files for T210</title>
<updated>2015-07-28T17:30:19+00:00</updated>
<author>
<name>Tom Warren</name>
<email>twarren@nvidia.com</email>
</author>
<published>2015-02-02T20:22:29+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=6c43f6c8d920caa1db01f5d0571a4d9ba720be15'/>
<id>6c43f6c8d920caa1db01f5d0571a4d9ba720be15</id>
<content type='text'>
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.

Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
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<pre>
All based off of Tegra124. As a Tegra210 board is brought
up, these may change a bit to match the HW more closely,
but probably 90% of this is identical to T124.

Note that since T210 is a 64-bit build, it has no SPL
component, and hence no cpu.c for Tegra210.

Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tegra: Add Tegra30 PCIe device tree node</title>
<updated>2014-12-18T20:19:21+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a1811bc5b999998ef5f42e2312a1140eb7cf3957'/>
<id>a1811bc5b999998ef5f42e2312a1140eb7cf3957</id>
<content type='text'>
Add the device tree node for the PCIe controller found on Tegra30 SoCs.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the device tree node for the PCIe controller found on Tegra30 SoCs.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tegra: Add Tegra20 PCIe device tree node</title>
<updated>2014-12-18T20:19:20+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=65d2465d5d4cdb347506438b226b01d6ef0eec79'/>
<id>65d2465d5d4cdb347506438b226b01d6ef0eec79</id>
<content type='text'>
Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tegra: dts: Add serial port details</title>
<updated>2014-09-10T19:00:02+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-09-04T22:27:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=c369139234c03b1494394d12cd27009f47aa6606'/>
<id>c369139234c03b1494394d12cd27009f47aa6606</id>
<content type='text'>
Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.

The console alias needs to be set up to indicate which port is used for
the console.

Also add a binding file since this is missing.

Series-changes; 5
- Add full serial port nodes from Linux tree (commit fc9d4dbe)
- Use /chosen/stdout-path instead of /aliases/console to specify the console

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Some Tegra device tree files do not include information about the serial
ports. Add this and also add information about the input clock speed.

The console alias needs to be set up to indicate which port is used for
the console.

Also add a binding file since this is missing.

Series-changes; 5
- Add full serial port nodes from Linux tree (commit fc9d4dbe)
- Use /chosen/stdout-path instead of /aliases/console to specify the console

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
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