u-boot.git/include/dt-bindings/clock, branch v2020.01 Unnamed repository; edit this file 'description' to name the repository. clk: mediatek: add driver for MT8518 2019-12-03T13:44:14+00:00 mingming lee mingming.lee@mediatek.com 2019-11-07T11:28:41+00:00 907240077516aec17529ac0ec9d16af8e91e167b Add clock driver for MediaTek MT8518 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com> 
Add clock driver for MediaTek MT8518 SoC.

Signed-off-by: mingming lee <mingming.lee@mediatek.com>
ARM: dts: stm32: DT alignment with kernel v5.3 2019-11-26T09:11:48+00:00 Patrick Delaunay patrick.delaunay@st.com 2019-11-06T15:16:32+00:00 e07a86b5e320113c31221029179db29e392fc090 Device tree and binding alignment with kernel v5.3 and converted to SPDX. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> 
Device tree and binding alignment with kernel v5.3
and converted to SPDX.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
rockchip: clk: Add clk driver for rk3308 2019-11-17T09:22:53+00:00 Finley Xiao finley.xiao@rock-chips.com 2019-11-14T03:21:13+00:00 fe9efbca7b99fd9303b25cf33cbd720603c88f27 Add clk controller driver for RK3308 SOC. This patch depends on Elaine's pll patch[0]. [0]http://patchwork.ozlabs.org/patch/1183718/ Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
Add clk controller driver for RK3308 SOC.

This patch depends on Elaine's pll patch[0].

[0]http://patchwork.ozlabs.org/patch/1183718/

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: clk: add px30 clock driver 2019-11-17T09:23:07+00:00 Kever Yang kever.yang@rock-chips.com 2019-07-11T08:42:16+00:00 d49a526750754cc93ffaa1182cfdf7ffa723e4b6 The px30 contains 2 separate clock controllers, pmucru and cru. Add drivers for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> 
The px30 contains 2 separate clock controllers, pmucru and cru.
Add drivers for them.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
imx: add dtsi for i.MX8MN 2019-11-05T09:27:18+00:00 Peng Fan peng.fan@nxp.com 2019-09-16T03:09:52+00:00 dadb072f1231850e0eb3cff53c88ff69211e099f Add dtsi for i.MX8MN Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Add dtsi for i.MX8MN

Signed-off-by: Peng Fan <peng.fan@nxp.com>
imx: update i.MX8MQ device trees 2019-11-03T16:04:16+00:00 Patrick Wildt patrick@blueri.se 2019-10-14T11:19:00+00:00 05737f35859756602e286cbd358f11b30cfb6383 This updates the i.MX8MQ device trees and, necessarily, also the i.MX8MQ clock bindings. These are taken verbatim from from the Linux kernel version v5.4-rc2, which three small changes which were already part of the previous device tree: * Keep the PSCI reserved memory range * Keep the alias for ethernet, so that the MAC address can be set * Keep the modified #include for the IOMUXC pins Signed-off-by: Patrick Wildt <patrick@blueri.se> Acked-by: Peng Fan <peng.fan@nxp.com> 
This updates the i.MX8MQ device trees and, necessarily, also the
i.MX8MQ clock bindings.  These are taken verbatim from from the
Linux kernel version v5.4-rc2, which three small changes which
were already part of the previous device tree:

 * Keep the PSCI reserved memory range
 * Keep the alias for ethernet, so that the MAC address can be set
 * Keep the modified #include for the IOMUXC pins

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Acked-by: Peng Fan <peng.fan@nxp.com>
Merge tag 'mips-pull-2019-10-25' of git://git.denx.de/u-boot-mips 2019-10-26T00:07:24+00:00 Tom Rini trini@konsulko.com 2019-10-26T00:07:24+00:00 ffc379b42c85466e1dd4c8fee8268801f26d2ab8 - bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs - bmips: various small fixes - mtmips: add new drivers for clock, reset-controller and pinctrl - mtmips: add support for high speed UART - mtmips: update/enhance drivers for SPI and ethernet - mtmips: add support for MMC 
- bmips: add BCRM NAND support for BCM6368, BCM6328, BCM6362 and BCM63268 SoCs
- bmips: various small fixes
- mtmips: add new drivers for clock, reset-controller and pinctrl
- mtmips: add support for high speed UART
- mtmips: update/enhance drivers for SPI and ethernet
- mtmips: add support for MMC
clk: add clock driver for MediaTek MT76x8 platform 2019-10-25T15:20:44+00:00 Weijie Gao weijie.gao@mediatek.com 2019-09-25T09:45:21+00:00 77ed3c42fee219fb50bca154b1ae36dbca8fc2e0 This patch adds a clock driver for MediaTek MT7628/7688 SoC. It provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
This patch adds a clock driver for MediaTek MT7628/7688 SoC.
It provides clock gate control as well as getting clock frequency for
CPU/SYS/XTAL and some peripherals.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
bmips: correct name characters 2019-10-25T15:20:43+00:00 Álvaro Fernández Rojas noltari@gmail.com 2019-08-30T10:00:42+00:00 f923c758e058e57b58e0ee780df4724fa023a958 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> 
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
dt-bindings: clock: zynqmp: Add clk header 2019-10-24T11:37:02+00:00 Rajan Vaja rajan.vaja@xilinx.com 2019-02-22T12:16:24+00:00 bdc27185bc1eee4cb1c73e90dfb6ed83bf0c332d Add dt clock header which can be included by dtses. And also use zynqmp-clk compatible string. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Add dt clock header which can be included by dtses. And also use zynqmp-clk
compatible string.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>