u-boot.git/include/dt-bindings/clock, branch v2021.04 Unnamed repository; edit this file 'description' to name the repository. Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi 2021-01-26T00:46:02+00:00 Tom Rini trini@konsulko.com 2021-01-26T00:46:02+00:00 e262b2973e22174da666038514d17f0f7171466b - New Allwinner H616 SoC support (sans Ethernet & USB) - H6 DT update - Tanix TX6 TV box support - OrangePi 3 support - OrangePi Zero2 (H616) support 
- New Allwinner H616 SoC support (sans Ethernet & USB)
- H6 DT update
- Tanix TX6 TV box support
- OrangePi 3 support
- OrangePi Zero2 (H616) support
arm: sunxi: add initial H616 DTSI and headers 2021-01-25T21:52:01+00:00 Jernej Skrabec jernej.skrabec@siol.net 2021-01-11T20:11:50+00:00 80b2c65bc26ad5e0b67bbca4796c3317cc7ce8cf This commit introduces H616 DTSI file and dt-bindings headers needed for device tree files. Files are taken from v3 Linux H616 support submission[1], as the H616 .dtsi file is not merged upstream yet. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/632082.html Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> 
This commit introduces H616 DTSI file and dt-bindings headers needed for
device tree files.

Files are taken from v3 Linux H616 support submission[1], as the
H616 .dtsi file is not merged upstream yet.

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/632082.html

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Merge tag 'mips-pull-2021-01-24' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips 2021-01-25T19:38:40+00:00 Tom Rini trini@konsulko.com 2021-01-25T19:38:40+00:00 c99be953e787cfb2414de67390427e00b6812240 - MIPS: add support for Mediatek MT7620 SoCs 
- MIPS: add support for Mediatek MT7620 SoCs
clk: add clock driver for MediaTek MT7620 SoC 2021-01-24T20:39:26+00:00 Weijie Gao weijie.gao@mediatek.com 2020-11-12T08:36:10+00:00 d9a5da72d790758dbad47787ab963c3ef2ee0cff This patch adds a clock driver for MediaTek MT7620 SoC. This driver provides clock gate control as well as getting clock frequency for CPU/SYS/XTAL and some peripherals. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
This patch adds a clock driver for MediaTek MT7620 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
arm: dts: imx8mq: sync dts from Linux Kernel 2021-01-23T10:30:31+00:00 Peng Fan peng.fan@nxp.com 2020-12-27T08:11:56+00:00 54bd9ddf21ba994187c1256730efabd5f4791650 Sync dts from Linux Kernel commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc") Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
arm: dts: imx8mp: sync dts from Linux Kernel 2021-01-23T10:30:31+00:00 Peng Fan peng.fan@nxp.com 2020-12-27T03:22:52+00:00 cf8842bc290201094bdeb9d8ed89f1b583469ebf Sync dts from Linux Kernel commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc") Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
arm: dts: imx8mn: sync dts from Linux Kernel 2021-01-23T10:30:30+00:00 Peng Fan peng.fan@nxp.com 2020-12-27T01:37:06+00:00 50d09531274211436d0d5038d4eefc8be12c0726 Sync dts from Linux Kernel commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc") Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Sync dts from Linux Kernel
commit f838f8d2b694cf9d524dc("mfd: ab8500-debugfs: Remove extraneous seq_putc")

Signed-off-by: Peng Fan <peng.fan@nxp.com>
clk: aspeed: Add AST2600 clock support 2021-01-18T20:14:56+00:00 Ryan Chen ryan_chen@aspeedtech.com 2020-12-14T05:54:23+00:00 a3c85990c36508cf7a5e7be82a275b2033400118 This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> 
This patch adds the clock control driver
for the AST2600 SoC.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
clk: mediatek: Add MT8183 clock driver 2021-01-18T20:14:13+00:00 Fabien Parent fparent@baylibre.com 2020-10-17T10:52:15+00:00 c9d7e79f02ef8184ab854fef5decc2f100447cef Add the topckgen, apmixedsys and infracfg clock driver for the MT8183 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> 
Add the topckgen, apmixedsys and infracfg clock driver for the MT8183
SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
clk: Add Microchip PolarFire SoC clock driver 2021-01-18T03:06:38+00:00 Padmarao Begari padmarao.begari@microchip.com 2021-01-15T02:50:38+00:00 2f27c9219e45c8abcbd53b0e66eff1f5bcae7c7e Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com> 
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Tested-by: Bin Meng <bin.meng@windriver.com>