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<title>u-boot.git/include/dt-bindings/clock, branch v2025.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>treewide: remove Qualcomm dt-binding headers that are available upstream</title>
<updated>2024-11-20T16:57:58+00:00</updated>
<author>
<name>Caleb Connolly</name>
<email>caleb.connolly@linaro.org</email>
</author>
<published>2024-11-13T04:33:32+00:00</published>
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<content type='text'>
Some dt-binding headers mask the upstream ones which can lead to build
failures, or worse: super weird bugs, if they get out of sync.

Remove these headers so our devicetree and binding headers will both be
in sync with upstream.

Reviewed-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
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<pre>
Some dt-binding headers mask the upstream ones which can lead to build
failures, or worse: super weird bugs, if they get out of sync.

Remove these headers so our devicetree and binding headers will both be
in sync with upstream.

Reviewed-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
Signed-off-by: Caleb Connolly &lt;caleb.connolly@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: Drop unused RZ/G2L devicetree bindings</title>
<updated>2024-11-10T18:36:39+00:00</updated>
<author>
<name>Paul Barker</name>
<email>paul.barker.ct@bp.renesas.com</email>
</author>
<published>2024-10-30T14:51:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=2badc6529bb19aa35ddbb061c5bdb24f33d76d6f'/>
<id>2badc6529bb19aa35ddbb061c5bdb24f33d76d6f</id>
<content type='text'>
We are now using the dts/upstream subtree for the RZ/G2L SoC family so
we can drop unused dt-bindings headers.

Signed-off-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
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<pre>
We are now using the dts/upstream subtree for the RZ/G2L SoC family so
we can drop unused dt-bindings headers.

Signed-off-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: renesas: Drop old unused clock DT headers</title>
<updated>2024-10-28T15:27:29+00:00</updated>
<author>
<name>Marek Vasut</name>
<email>marek.vasut+renesas@mailbox.org</email>
</author>
<published>2024-10-27T02:04:30+00:00</published>
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<content type='text'>
Renesas R-Car systems use mainline Linux DTs for U-Boot via OF_UPSTREAM,
which also includes headers from dts/upstream/include/dt-bindings/clock .
Remove unused legacy DT header files from include/dt-bindings/clock .

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Reviewed-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
Reviewed-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
</content>
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<pre>
Renesas R-Car systems use mainline Linux DTs for U-Boot via OF_UPSTREAM,
which also includes headers from dts/upstream/include/dt-bindings/clock .
Remove unused legacy DT header files from include/dt-bindings/clock .

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
Reviewed-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
Reviewed-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: H616: switch to OF_UPSTREAM</title>
<updated>2024-10-09T23:23:41+00:00</updated>
<author>
<name>Andre Przywara</name>
<email>andre.przywara@arm.com</email>
</author>
<published>2024-08-07T23:08:45+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9c4b44d1e3e988b3db6a631c436498e186297b31'/>
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<content type='text'>
With the recent "old-style sunxi" sync and the penultimate OF_UPSTREAM DT
update, both directories were based on the same v6.10 kernel tree.
And while there is one subtle difference in many Allwinner SoC's DT
files, the H616 ones turn out to be identical.

Remove the old copies of the H616 related .dts and .dtsi files, and
switch the whole H616 SoC over to use OF_UPSTREAM. This immediately
benefits from the recent upstream DT update, to kernel v6.11.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</content>
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<pre>
With the recent "old-style sunxi" sync and the penultimate OF_UPSTREAM DT
update, both directories were based on the same v6.10 kernel tree.
And while there is one subtle difference in many Allwinner SoC's DT
files, the H616 ones turn out to be identical.

Remove the old copies of the H616 related .dts and .dtsi files, and
switch the whole H616 SoC over to use OF_UPSTREAM. This immediately
benefits from the recent upstream DT update, to kernel v6.11.

Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: clk: import header for clock controller of sophgo CV1800B</title>
<updated>2024-09-11T12:32:06+00:00</updated>
<author>
<name>Kongyang Liu</name>
<email>seashell11234455@gmail.com</email>
</author>
<published>2024-06-11T09:41:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=bd2f42230ed4f9e732e101a5fab0832a55b4b1c5'/>
<id>bd2f42230ed4f9e732e101a5fab0832a55b4b1c5</id>
<content type='text'>
Import header file of sophgo cv1800b clock controller from kernel

Signed-off-by: Kongyang Liu &lt;seashell11234455@gmail.com&gt;
Link: https://lore.kernel.org/all/IA1PR20MB4953637E7A6C121D7A700F1CBB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</content>
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<pre>
Import header file of sophgo cv1800b clock controller from kernel

Signed-off-by: Kongyang Liu &lt;seashell11234455@gmail.com&gt;
Link: https://lore.kernel.org/all/IA1PR20MB4953637E7A6C121D7A700F1CBB8BA@IA1PR20MB4953.namprd20.prod.outlook.com/
Reviewed-by: Leo Yu-Chi Liang &lt;ycliang@andestech.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'v2024.10-rc3' into next</title>
<updated>2024-08-20T00:24:58+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-08-20T00:24:58+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=158cf0270cb6691bc7f58fbeb4c6b8b603957bfe'/>
<id>158cf0270cb6691bc7f58fbeb4c6b8b603957bfe</id>
<content type='text'>
Prepare v2024.10-rc3
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<pre>
Prepare v2024.10-rc3
</pre>
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</content>
</entry>
<entry>
<title>Merge patch series "clk: mediatek: mt7622: clk migration for OF_UPSTREAM"</title>
<updated>2024-08-19T22:15:51+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2024-08-19T22:15:47+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=aa2efb08732aa4daded61fca8e488eb211b28ce4'/>
<id>aa2efb08732aa4daded61fca8e488eb211b28ce4</id>
<content type='text'>
Christian Marangi &lt;ansuelsmth@gmail.com&gt; says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
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<pre>
Christian Marangi &lt;ansuelsmth@gmail.com&gt; says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: add missing A1/2SYS clock ID</title>
<updated>2024-08-19T22:15:26+00:00</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:26+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a73dce6c8296fb1fa53932af8872a11d1404c4e6'/>
<id>a73dce6c8296fb1fa53932af8872a11d1404c4e6</id>
<content type='text'>
Add missing A1/2SYS clock ID just as a reference for OF_UPSTREAM
support. These clocks are not defined and are not usable as current
clock topckgen OPs doesn't support gates.

These special node won't ever be used by uboot hence just add them for
reference.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
</content>
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<pre>
Add missing A1/2SYS clock ID just as a reference for OF_UPSTREAM
support. These clocks are not defined and are not usable as current
clock topckgen OPs doesn't support gates.

These special node won't ever be used by uboot hence just add them for
reference.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
Tested-by: Frank Wunderlich &lt;frank-w@public-files.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: add missing clock PERIBUS_SEL clock</title>
<updated>2024-08-19T22:15:26+00:00</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:25+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=105c78844a6cf72eefbfd614fc52da92bc0341f1'/>
<id>105c78844a6cf72eefbfd614fc52da92bc0341f1</id>
<content type='text'>
Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also
convert pericfg to mux + gate implementation as now we have also mux on
top of gates.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
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<pre>
Add missing PERIBUS_SEL clock to match upstream linux clk ID order. Also
convert pericfg to mux + gate implementation as now we have also mux on
top of gates.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>clk: mediatek: mt7622: add missing clock PERI_UART4_PD</title>
<updated>2024-08-19T22:15:26+00:00</updated>
<author>
<name>Christian Marangi</name>
<email>ansuelsmth@gmail.com</email>
</author>
<published>2024-08-03T08:43:24+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a776493f4b4b51515db456e635709a93e256dacd'/>
<id>a776493f4b4b51515db456e635709a93e256dacd</id>
<content type='text'>
Add missing clock PERI_UART4_PD for peri clock gates. This is needed to
match upstream linux clk ID in preparation for OF_UPSTREAM.
Also convert infracfg to mux + gate implementation as now we have mux on
top of gates.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</content>
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<pre>
Add missing clock PERI_UART4_PD for peri clock gates. This is needed to
match upstream linux clk ID in preparation for OF_UPSTREAM.
Also convert infracfg to mux + gate implementation as now we have mux on
top of gates.

Signed-off-by: Christian Marangi &lt;ansuelsmth@gmail.com&gt;
</pre>
</div>
</content>
</entry>
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