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<title>u-boot.git/include/dt-bindings/gpio, branch v2016.09</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>arm: dts: update DTS files for meson-gxbb and odroid-c2</title>
<updated>2016-09-06T17:18:19+00:00</updated>
<author>
<name>Beniamino Galvani</name>
<email>b.galvani@gmail.com</email>
</author>
<published>2016-08-16T09:49:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dd83840e5efc297b184196f2603f537a167f85e4'/>
<id>dd83840e5efc297b184196f2603f537a167f85e4</id>
<content type='text'>
Import DTS files and dt-bindings includes from Linux 4.8-rc1.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Import DTS files and dt-bindings includes from Linux 4.8-rc1.

Signed-off-by: Beniamino Galvani &lt;b.galvani@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
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</content>
</entry>
<entry>
<title>gpio: add Tegra186 GPIO driver</title>
<updated>2016-05-31T16:54:24+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-05-25T20:38:51+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=074a1fdd27953aacb59346c83baaf443335ea04e'/>
<id>074a1fdd27953aacb59346c83baaf443335ea04e</id>
<content type='text'>
Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.

The DT binding is already present in the Linux kernel (in linux-next via
the Tegra tree so far).

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt; # v1
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
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<pre>
Tegra186's GPIO controller register layout is significantly different from
previous chips, so add a new driver for it. In fact, there are two
different GPIO controllers in Tegra186 that share a similar register
layout, but very different port mapping. This driver covers both.

The DT binding is already present in the Linux kernel (in linux-next via
the Tegra tree so far).

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt; # v1
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tegra: fix naming in GPIO DT binding header</title>
<updated>2016-05-31T16:53:56+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2016-05-12T18:07:40+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e6bf0ca0e2ef8d87d754f788be1b9b5d58c01860'/>
<id>e6bf0ca0e2ef8d87d754f788be1b9b5d58c01860</id>
<content type='text'>
According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs,
not into /banks/. Fix &lt;dt-bindings/gpio/tegra-gpio.h&gt; to correctly reflect
this naming convention. While this seems like silly churn, it will become
slightly more important once we introduce the GPIO binding for upcoming
Tegra chips. This mirrors an identical commit in the Linux kernel.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
<content type='xhtml'>
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<pre>
According to the Tegra TRM, GPIOs are aggregated into /ports/ of 8 GPIOs,
not into /banks/. Fix &lt;dt-bindings/gpio/tegra-gpio.h&gt; to correctly reflect
this naming convention. While this seems like silly churn, it will become
slightly more important once we introduce the GPIO binding for upcoming
Tegra chips. This mirrors an identical commit in the Linux kernel.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: broadwell: Add a pinctrl driver</title>
<updated>2016-03-17T02:27:26+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2016-03-12T05:07:20+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b24f5c4f27bf6a473fc9a3937a2bbf6ddf0fb104'/>
<id>b24f5c4f27bf6a473fc9a3937a2bbf6ddf0fb104</id>
<content type='text'>
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
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<pre>
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: gpio: add pinctrl support from the device tree</title>
<updated>2015-06-04T09:32:08+00:00</updated>
<author>
<name>Gabriel Huau</name>
<email>contact@huau-gabriel.fr</email>
</author>
<published>2015-05-26T05:27:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5318f18d2c002f505054b90bb95ba7c53532eedf'/>
<id>5318f18d2c002f505054b90bb95ba7c53532eedf</id>
<content type='text'>
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau &lt;contact@huau-gabriel.fr&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau &lt;contact@huau-gabriel.fr&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>tegra: dts: Bring in GPIO bindings from linux</title>
<updated>2014-06-20T17:56:33+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2014-06-12T05:29:52+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=8946034a311f80ca913f99f5c5691983d8b619c6'/>
<id>8946034a311f80ca913f99f5c5691983d8b619c6</id>
<content type='text'>
These files are taken from Linux 3.14.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</content>
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<pre>
These files are taken from Linux 3.14.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
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