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<title>u-boot.git/include/dt-bindings/pinctrl, branch v2021.01</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/include/dt-bindings/pinctrl?h=v2021.01</id>
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<updated>2020-10-08T15:42:36Z</updated>
<entry>
<title>pinctrl: Add support for Kendryte K210 FPIOA</title>
<updated>2020-10-08T15:42:36Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-09-14T15:01:58Z</published>
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<id>urn:sha1:7224d5ccf8e1d2552e2994c5d55769c334231c08</id>
<content type='text'>
The Fully-Programmable Input/Output Array (FPIOA) device controls pin
multiplexing on the K210. The FPIOA can remap any supported function to any
multifunctional IO pin. It can also perform basic GPIO functions, such as
reading the current value of a pin. However, GPIO functionality remains
largely unimplemented (in favor of the dedicated GPIO peripherals).

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>test: pinmux: Add test for pin muxing</title>
<updated>2020-10-08T15:42:36Z</updated>
<author>
<name>Sean Anderson</name>
<email>seanga2@gmail.com</email>
</author>
<published>2020-09-14T15:01:57Z</published>
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<id>urn:sha1:7f0f1806e3a474dc15b6bad806b4afa967447774</id>
<content type='text'>
This extends the pinctrl-sandbox driver to support pin muxing, and adds a
test for that behaviour. The test is done in C and not python (like the
existing tests for the pinctrl uclass) because it needs to call
pinctrl_select_state.  Another option could be to add a command that
invokes pinctrl_select_state and then test everything in
test/py/tests/test_pinmux.py.

The pinctrl-sandbox driver now mimics the way that many pinmux devices
work.  There are two groups of pins which are muxed together, as well as
four pins which are muxed individually. I have tried to test all normal
paths. However, very few error cases are explicitly checked for.

Signed-off-by: Sean Anderson &lt;seanga2@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: add ns3 pads definition</title>
<updated>2020-07-29T14:37:11Z</updated>
<author>
<name>Rayagonda Kokatanur</name>
<email>rayagonda.kokatanur@broadcom.com</email>
</author>
<published>2020-07-15T17:23:02Z</published>
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<id>urn:sha1:3ce080862576c482a8b128a36869cc49a4b3bef1</id>
<content type='text'>
Add NS3 pads definitions.

Signed-off-by: Rayagonda Kokatanur &lt;rayagonda.kokatanur@broadcom.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: imxrt1020: remove useless comment</title>
<updated>2020-05-01T11:46:22Z</updated>
<author>
<name>Giulio Benetti</name>
<email>giulio.benetti@benettiengineering.com</email>
</author>
<published>2020-04-20T15:48:12Z</published>
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<id>urn:sha1:de0e7cba41f4dde3ae6bc8a405d760cc178c661b</id>
<content type='text'>
A comment note has been left after completing pinctrl listing, so let's
remove it since it's useless.

Signed-off-by: Giulio Benetti &lt;giulio.benetti@benettiengineering.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: add i.MXRT1020 pins definition</title>
<updated>2020-04-18T12:54:51Z</updated>
<author>
<name>Giulio Benetti</name>
<email>giulio.benetti@benettiengineering.com</email>
</author>
<published>2020-02-18T19:02:54Z</published>
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<id>urn:sha1:7787330200526023f49b4d60869a1c91e908132a</id>
<content type='text'>
Add i.MXRT1020 pins definition.

Signed-off-by: Giulio Benetti &lt;giulio.benetti@benettiengineering.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: imxrt1050: add dtsi file</title>
<updated>2020-01-14T21:53:59Z</updated>
<author>
<name>Giulio Benetti</name>
<email>giulio.benetti@benettiengineering.com</email>
</author>
<published>2020-01-10T14:47:04Z</published>
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<id>urn:sha1:e12b737e937ead3ed94b16e267ccfe877714cd06</id>
<content type='text'>
Add dtsi file for i.MXRT1050.

Signed-off-by: Giulio Benetti &lt;giulio.benetti@benettiengineering.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E</title>
<updated>2019-07-27T01:49:28Z</updated>
<author>
<name>Lokesh Vutla</name>
<email>lokeshvutla@ti.com</email>
</author>
<published>2019-06-13T04:59:52Z</published>
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<id>urn:sha1:382f1dda977e9f5a1fba23cb6b7fed136c767a4c</id>
<content type='text'>
Add pinctrl macros for J721E SoC. These macro definitions are
similar to that of AM6, but adding new definitions to avoid
any naming confusions in the soc dts files.

Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Signed-off-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: stm32: add new entry for package information</title>
<updated>2019-07-12T09:18:53Z</updated>
<author>
<name>Patrick Delaunay</name>
<email>patrick.delaunay@st.com</email>
</author>
<published>2019-07-05T15:20:12Z</published>
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<id>urn:sha1:d3f077b3490bcf4f202d85a195cede591f6f3995</id>
<content type='text'>
Add "st,package" entry. Possibles values are:
-STM32MP_PKG_AA for LFBGA448 (18*18) package
-STM32MP_PKG_AB for LFBGA354 (16*16) package
-STM32MP_PKG_AC for TFBGA361 (12*12) package
-STM32MP_PKG_AD for TFBGA257 (10*10) package

see Linux commit 966d9b928f626a54a0c27c0fdae1e3dfe9bab416
for v5.2-rc1

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>fdt: update bcm283x device tree sources to Linux 5.1-rc6 state</title>
<updated>2019-06-12T10:23:46Z</updated>
<author>
<name>Heinrich Schuchardt</name>
<email>xypron.glpk@gmx.de</email>
</author>
<published>2019-04-28T04:46:57Z</published>
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<id>urn:sha1:143256b353c4d2ad1cf5e5e63b38410188b35e49</id>
<content type='text'>
Updating the bcm283x device tree sources adds the device trees for

- Raspberry Pi 3 Model A+
- Raspberry Pi 3 Model B+
- Raspberry Pi Compute Module IO board rev1
- Raspberry Pi Compute Module 3 IO board V3.0
- Raspberry Pi Zero

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
Signed-off-by: Matthias Brugger &lt;mbrugger@suse.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: renesas: Add RZ/A1 platform code</title>
<updated>2019-05-07T03:41:32Z</updated>
<author>
<name>Chris Brandt</name>
<email>chris.brandt@renesas.com</email>
</author>
<published>2017-08-23T19:53:59Z</published>
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<id>urn:sha1:3529596442c9cf588b7b8a3e7573f0ff9d8ed350</id>
<content type='text'>
Add platform code and DTs for Renesas RZ/A1 R7S72100 SoC.
Distinguishing feature of this SoC is that it has up to
10 MiB of on-SoC static RAM (SRAM).

The DTs are imported from Linux 5.0.11, commit d5a2675b207d .

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Chris Brandt &lt;chris.brandt@renesas.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
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