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<title>u-boot.git/include/dt-bindings/pinctrl, branch v2024.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/include/dt-bindings/pinctrl?h=v2024.04</id>
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<updated>2023-12-19T16:42:03Z</updated>
<entry>
<title>Merge patch series "Add support for MediaTek MT8365 EVK Board"</title>
<updated>2023-12-19T16:42:03Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-12-19T15:09:14Z</published>
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<id>urn:sha1:9cfef5fcfb58aceca8f8599643bfe58710567575</id>
<content type='text'>
Julien Masson &lt;jmasson@baylibre.com&gt; says:

This patch series add the support for the MediaTek MT8365 EVK Board [1].
Most of the code have been copied/adapted from Linux tag v6.7-rc2.

For now we only enable/test these features:
Boot, UART, Watchdog and MMC.

[trini: This includes two clocks not listed in the Linux binding, which
 needs resyncing later]
</content>
</entry>
<entry>
<title>dt-bindings: clock: add Mediatek MT8365 pinctrl bindings</title>
<updated>2023-12-19T15:09:06Z</updated>
<author>
<name>Julien Masson</name>
<email>jmasson@baylibre.com</email>
</author>
<published>2023-12-04T10:48:56Z</published>
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<id>urn:sha1:5679eccb83f29c1fa149655fd798b229b2fc1753</id>
<content type='text'>
This adds the pinctrl bindings for Mediatek MT8365 SoC based on the
dt-bindings in Linux tag v6.7-rc2.
(commit 8b4c397d88d97d4fd9c3f3527aa66688b1a3387a)

Signed-off-by: Julien Masson &lt;jmasson@baylibre.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v2024.01-rc3' into next</title>
<updated>2023-11-20T14:19:50Z</updated>
<author>
<name>Tom Rini</name>
<email>trini@konsulko.com</email>
</author>
<published>2023-11-20T14:19:50Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=dca7a8958f8d0dbd53072caa4353353e062d80ca'/>
<id>urn:sha1:dca7a8958f8d0dbd53072caa4353353e062d80ca</id>
<content type='text'>
Prepare v2024.01-rc3
</content>
</entry>
<entry>
<title>ARM: dts: stm32: Add STM32MP257F Evaluation board support</title>
<updated>2023-11-13T09:55:38Z</updated>
<author>
<name>Patrice Chotard</name>
<email>patrice.chotard@foss.st.com</email>
</author>
<published>2023-10-27T14:43:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=970d1673b016ae013839d7bcd69a17601b450304'/>
<id>urn:sha1:970d1673b016ae013839d7bcd69a17601b450304</id>
<content type='text'>
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC,
with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC,
SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...

Sync device tree with kernel v6.6-rc1.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@foss.st.com&gt;
Reviewed-by: Patrick Delaunay &lt;patrick.delaunay@foss.st.com&gt;
</content>
</entry>
<entry>
<title>tree-wide: Replace http:// link with https:// link for ti.com</title>
<updated>2023-11-10T16:01:50Z</updated>
<author>
<name>Nishanth Menon</name>
<email>nm@ti.com</email>
</author>
<published>2023-11-01T20:56:03Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a94a4071d449e12c9fb5ac37d6362d22efcb27da'/>
<id>urn:sha1:a94a4071d449e12c9fb5ac37d6362d22efcb27da</id>
<content type='text'>
Replace instances of http://www.ti.com with https://www.ti.com

Signed-off-by: Nishanth Menon &lt;nm@ti.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Add RZ/G2L PFC bindings</title>
<updated>2023-10-16T13:46:17Z</updated>
<author>
<name>Paul Barker</name>
<email>paul.barker.ct@bp.renesas.com</email>
</author>
<published>2023-10-16T09:25:25Z</published>
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<id>urn:sha1:4517bd14adf96fd9fab0d1abed51fdc7153c1395</id>
<content type='text'>
Import bindings for the Port Function Control (PFC) module in the
Renesas RZ/G2L SoC family.

This patch is based on the dt-bindings in Linux v6.5
(commit 52e12027d50affbf60c6c9c64db8017391b0c22e).

Signed-off-by: Paul Barker &lt;paul.barker.ct@bp.renesas.com&gt;
Reviewed-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt;
Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: add R906G032 driver</title>
<updated>2023-05-13T02:01:30Z</updated>
<author>
<name>Ralph Siemsen</name>
<email>ralph.siemsen@linaro.org</email>
</author>
<published>2023-05-13T01:36:52Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=e4aea57fa773ada9443176e2e39af0b4e1750c65'/>
<id>urn:sha1:e4aea57fa773ada9443176e2e39af0b4e1750c65</id>
<content type='text'>
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.

This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.

Signed-off-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Reviewed-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions</title>
<updated>2023-04-20T08:08:44Z</updated>
<author>
<name>Jianlong Huang</name>
<email>jianlong.huang@starfivetech.com</email>
</author>
<published>2023-03-29T03:42:14Z</published>
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<id>urn:sha1:d60f38493837d70a66cb9655169459d65dbe5fca</id>
<content type='text'>
Add pinctrl definitions for StarFive JH7110 SoC.

Signed-off-by: Kuan Lim Lee &lt;kuanlim.lee@linux.starfivetech.com&gt;
Signed-off-by: Emil Renner Berthing &lt;kernel@esmil.dk&gt;
Signed-off-by: Jianlong Huang &lt;jianlong.huang@starfivetech.com&gt;
Signed-off-by: Yanhong Wang &lt;yanhong.wang@starfivetech.com&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
</content>
</entry>
<entry>
<title>pinctrl-snapdragon: Get rid of custom drive-strength values</title>
<updated>2023-02-10T17:50:00Z</updated>
<author>
<name>Sumit Garg</name>
<email>sumit.garg@linaro.org</email>
</author>
<published>2023-02-01T13:58:52Z</published>
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<id>urn:sha1:56443285f2add2161c97f413ffa25c5024ee1ef9</id>
<content type='text'>
Use standard pinconf drive-strength values from Linux DT bindings rather
than ones based on custom u-boot header. These changes are in direction
to make u-boot DTs for Qcom SoCs to be compatible with standard Linux
DT bindings.

Also, add support for pinconf bias-pull-up.

Signed-off-by: Sumit Garg &lt;sumit.garg@linaro.org&gt;
</content>
</entry>
<entry>
<title>arm: dts: introduce am62a7 dtbs from linux kernel</title>
<updated>2022-12-09T19:10:28Z</updated>
<author>
<name>Bryan Brattlof</name>
<email>bb@ti.com</email>
</author>
<published>2022-11-04T00:13:51Z</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=253802912a65fde6ba9328462ef4b8574932c8f3'/>
<id>urn:sha1:253802912a65fde6ba9328462ef4b8574932c8f3</id>
<content type='text'>
Introduce the basic am62a7 SoC dtbs from the v6.1-rc3 tag of the linux
kernel along with the new am62a specific pinmux definition that we will
use to generate the dtbs for the u-boot-spl and u-boot binaries

Co-developed-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Signed-off-by: Vignesh Raghavendra &lt;vigneshr@ti.com&gt;
Signed-off-by: Bryan Brattlof &lt;bb@ti.com&gt;
</content>
</entry>
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