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<title>u-boot.git/include/dt-bindings, branch v2015.07</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/'/>
<entry>
<title>ti: Add SPDX license identifier to omap.h</title>
<updated>2015-07-08T22:26:41+00:00</updated>
<author>
<name>Simon Glass</name>
<email>sjg@chromium.org</email>
</author>
<published>2015-06-30T22:03:02+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=f41d6b7d4295e2a5f33cbdca7b5b2518fac42934'/>
<id>f41d6b7d4295e2a5f33cbdca7b5b2518fac42934</id>
<content type='text'>
This also came from Linux - according to this thread it has a GPL v2
license like arch/arm/mach-omap2/mux.h:

http://lists.denx.de/pipermail/u-boot/2015-June/217827.html

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reported-by: Ingrid Viitanen &lt;ingrid.viitanen@nokia.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
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<pre>
This also came from Linux - according to this thread it has a GPL v2
license like arch/arm/mach-omap2/mux.h:

http://lists.denx.de/pipermail/u-boot/2015-June/217827.html

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reported-by: Ingrid Viitanen &lt;ingrid.viitanen@nokia.com&gt;
Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: gpio: add pinctrl support from the device tree</title>
<updated>2015-06-04T09:32:08+00:00</updated>
<author>
<name>Gabriel Huau</name>
<email>contact@huau-gabriel.fr</email>
</author>
<published>2015-05-26T05:27:37+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=5318f18d2c002f505054b90bb95ba7c53532eedf'/>
<id>5318f18d2c002f505054b90bb95ba7c53532eedf</id>
<content type='text'>
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau &lt;contact@huau-gabriel.fr&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
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<pre>
Every pin can be configured now from the device tree. A dt-bindings
has been added to describe the different property available.

Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975
Signed-off-by: Gabriel Huau &lt;contact@huau-gabriel.fr&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>x86: Refactor PIRQ routing support</title>
<updated>2015-06-04T08:39:39+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-05-25T14:35:04+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9c7dea602edd9027848d312e9b3b69f06c15f163'/>
<id>9c7dea602edd9027848d312e9b3b69f06c15f163</id>
<content type='text'>
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
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<pre>
PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sandbox: dts: add sandbox_pmic.dtsi and include it to sandbox.dts and test.dts</title>
<updated>2015-05-15T01:59:21+00:00</updated>
<author>
<name>Przemyslaw Marczak</name>
<email>p.marczak@samsung.com</email>
</author>
<published>2015-05-13T11:38:35+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=9038cd531382e94cc6d4daa9e81f70491030aa38'/>
<id>9038cd531382e94cc6d4daa9e81f70491030aa38</id>
<content type='text'>
This commit adds dtsi file for Sandbox PMIC.
It fully describes the PMIC by:
- i2c emul node - with a default settings of 16 registers
- 2x buck regulator nodes
- 2x ldo regulator nodes

The default register settings are set with preprocessor macros:
- VAL2REG(min[uV/uA], step[uV/uA], val[uV/uA])
- VAL2OMREG(mode id)
Both defined in file:
- include/dt-bindings/pmic/sandbox_pmic.h

The Voltage ranges of each regulator can be found in:
- include/power/sandbox_pmic.h

The new file is included into:
- sandbox.dts
- test.dts

Signed-off-by: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on sandbox:
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This commit adds dtsi file for Sandbox PMIC.
It fully describes the PMIC by:
- i2c emul node - with a default settings of 16 registers
- 2x buck regulator nodes
- 2x ldo regulator nodes

The default register settings are set with preprocessor macros:
- VAL2REG(min[uV/uA], step[uV/uA], val[uV/uA])
- VAL2OMREG(mode id)
Both defined in file:
- include/dt-bindings/pmic/sandbox_pmic.h

The Voltage ranges of each regulator can be found in:
- include/power/sandbox_pmic.h

The new file is included into:
- sandbox.dts
- test.dts

Signed-off-by: Przemyslaw Marczak &lt;p.marczak@samsung.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
Tested on sandbox:
Tested-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>sunxi: dts: Sync all dts files with upstream kernel</title>
<updated>2015-05-04T14:51:54+00:00</updated>
<author>
<name>Hans de Goede</name>
<email>hdegoede@redhat.com</email>
</author>
<published>2015-04-15T17:03:49+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=53ab4af34e4e4242809114580320d2faa150b336'/>
<id>53ab4af34e4e4242809114580320d2faa150b336</id>
<content type='text'>
Bring all the sunxi dts files (and update existing ones) from
mripard/sunxi/dt-for-4.1 (which will be merged into upstream master any
day now). This is necessary so that we can move all sunxi boards over to
the driver model.

Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Ian Campbell &lt;ijc@hellion.org.uk&gt;
</content>
<content type='xhtml'>
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<pre>
Bring all the sunxi dts files (and update existing ones) from
mripard/sunxi/dt-for-4.1 (which will be merged into upstream master any
day now). This is necessary so that we can move all sunxi boards over to
the driver model.

Signed-off-by: Hans de Goede &lt;hdegoede@redhat.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
Acked-by: Ian Campbell &lt;ijc@hellion.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: Add Intel Quark MRC bindings</title>
<updated>2015-02-06T19:07:44+00:00</updated>
<author>
<name>Bin Meng</name>
<email>bmeng.cn@gmail.com</email>
</author>
<published>2015-02-05T15:42:27+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=b1420c813074d39cd2452d7bc45374561d1cf223'/>
<id>b1420c813074d39cd2452d7bc45374561d1cf223</id>
<content type='text'>
Add standard dt-bindings macros to be used by Intel Quark MRC node.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add standard dt-bindings macros to be used by Intel Quark MRC node.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Acked-by: Simon Glass &lt;sjg@chromium.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tegra: Add Tegra30 PCIe device tree node</title>
<updated>2014-12-18T20:19:21+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:16+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=a1811bc5b999998ef5f42e2312a1140eb7cf3957'/>
<id>a1811bc5b999998ef5f42e2312a1140eb7cf3957</id>
<content type='text'>
Add the device tree node for the PCIe controller found on Tegra30 SoCs.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
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<pre>
Add the device tree node for the PCIe controller found on Tegra30 SoCs.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tegra: Add Tegra20 PCIe device tree node</title>
<updated>2014-12-18T20:19:20+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:13+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=65d2465d5d4cdb347506438b226b01d6ef0eec79'/>
<id>65d2465d5d4cdb347506438b226b01d6ef0eec79</id>
<content type='text'>
Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the device tree node for the PCIe controller found on Tegra20 SoCs.

Acked-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: tegra: Implement XUSB pad controller</title>
<updated>2014-12-18T20:19:20+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2014-12-10T05:25:09+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=79c7a90f6c642c27da3de5c134816be7f0405f1d'/>
<id>79c7a90f6c642c27da3de5c134816be7f0405f1d</id>
<content type='text'>
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</content>
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<pre>
This controller was introduced on Tegra114 to handle XUSB pads. On
Tegra124 it is also used for PCIe and SATA pin muxing and PHY control.
Only the Tegra124 PCIe and SATA functionality is currently implemented,
with weak symbols on Tegra114.

Tegra20 and Tegra30 also provide weak symbols for these functions so
that drivers can use the same API irrespective of which SoC they're
being built for.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Tom Warren &lt;twarren@nvidia.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branch 'master' of git://git.denx.de/u-boot-socfpga</title>
<updated>2014-12-16T14:41:00+00:00</updated>
<author>
<name>Tom Rini</name>
<email>trini@ti.com</email>
</author>
<published>2014-12-16T14:41:00+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3bfbf32b6fe5e2d4605bc7ee99d1844b572662c2'/>
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<pre>
</pre>
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</content>
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