u-boot.git/include/dt-bindings, branch v2019.04 Unnamed repository; edit this file 'description' to name the repository. clk: Add SiFive FU540 PRCI clock driver 2019-02-27T01:12:33+00:00 Anup Patel Anup.Patel@wdc.com 2019-02-25T08:14:49+00:00 c40b6df87fc0193a7184ada9f53aaf57cdec0cdf Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> 
Add driver code for the SiFive FU540 PRCI IP block.  This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra <wesley@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
sound: Add support for Intel HDA 2019-02-20T07:27:09+00:00 Simon Glass sjg@chromium.org 2019-02-17T03:24:55+00:00 2ca471379b471dc0d31459974d7cc4b54c824956 The Intel High-definition Audio is a newer-generation audio system which provides for transfer of a large number of audio stream, each containing up to 16 channels. Add support for HDA as a library which can be used by other drivers. U-Boot currently uses only two channels (stereo). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
The Intel High-definition Audio is a newer-generation audio system which
provides for transfer of a large number of audio stream, each containing
up to 16 channels.

Add support for HDA as a library which can be used by other drivers.
U-Boot currently uses only two channels (stereo).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
dts: stm32mp1: clock tree update 2019-02-09T12:50:57+00:00 Patrick Delaunay patrick.delaunay@st.com 2019-01-30T12:07:05+00:00 e74b74c52876d776dda7a7ee5e2a8d555eaa5c4f - Add st,digbypass on clk_hse node (needed for board rev.C) - MLAHB/AHB max frequency increased from 200 to 209MHz, with: - PLL3P set to 208.8MHz for MCU sub-system - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S - PLL4P set to 99MHz for SDMMC and SPDIFRX - PLL4Q set to 74.25MHz for EVAL board Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> 
- Add st,digbypass on clk_hse node (needed for board rev.C)
- MLAHB/AHB max frequency increased from 200 to 209MHz, with:
  - PLL3P set to 208.8MHz for MCU sub-system
  - PLL3Q set to 24.57MHz for 48kHz SAI/SPI2S
  - PLL3R set to 11.29MHz for 44.1kHz SAI/SPI2S
  - PLL4P set to 99MHz for SDMMC and SPDIFRX
  - PLL4Q set to 74.25MHz for EVAL board

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
poplar: sync up device tree with kernel 4.20 2019-01-25T17:12:56+00:00 Shawn Guo shawn.guo@linaro.org 2019-01-17T04:09:50+00:00 8eef803a276c4b586ba5ad82e13485809934ffed It adds missing pinctrl headers, updates clock header and sync up Poplar device tree with kernel 4.20 release. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> 
It adds missing pinctrl headers, updates clock header and sync up Poplar
device tree with kernel 4.20 release.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
sunxi: A64: Update sun50i-a64-ccu.h 2019-01-18T16:49:09+00:00 Jagan Teki jagan@amarulasolutions.com 2018-12-29T18:29:08+00:00 aa86bf90d11fe4c6d4c5ce20895f734ca59aabb7 Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree: commit 679294497be31596e1c9c61507746d72b6b05f26 Author: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz> Date: Wed Sep 26 19:48:24 2018 +0000 arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay This should be a part of previous sync patch from commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691 Author: Andre Przywara <andre.przywara@arm.com> Date: Mon Oct 29 00:56:47 2018 +0000 sunxi: A64: Update .dts/.dtsi files Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> 
Update sun50i-a64-ccu.h from the Linux sunxi/dt64-for-4.20 tree:
commit 679294497be31596e1c9c61507746d72b6b05f26
Author: Rodrigo Exterckötter Tjäder <rodrigo@tjader.xyz>
Date:   Wed Sep 26 19:48:24 2018 +0000
    arm64: dts: allwinner: a64: a64-olinuxino: set the PHY TX delay

This should be a part of previous sync patch from
commit 1b39a1834ed182bbd8036a5cd74a9ea111fa4691
Author: Andre Przywara <andre.przywara@arm.com>
Date:   Mon Oct 29 00:56:47 2018 +0000

    sunxi: A64: Update .dts/.dtsi files

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
ARM: dts: sun8i: Update A80 dts(i) from Linux-v4.18-rc3 2019-01-18T16:49:09+00:00 Jagan Teki jagan@amarulasolutions.com 2019-01-11T10:52:57+00:00 8dcc7e69224f898272dbbbba2d9a1c5efaa28304 Update all A80 devicetree dtsi and dtsi files from Linux-v4.18-rc3 with below commits. arch/arm/boot/dts/sun9i-a80*: commit 190e3138f9577885691540dca59c2f07540bde04 Merge: cafc87023b0d a7affb13b271 Author: Arnd Bergmann <arnd@arndb.de> Date: Tue Mar 27 14:58:00 2018 +0200 Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt include/dt-bindings/*/sun9i-a80-*: commit 783ab76ae553abc23f80ef7511052d055697531b Author: Chen-Yu Tsai <wens@csie.org> Date: Sat Jan 28 20:22:36 2017 +0800 clk: sunxi-ng: Add A80 Display Engine CCU Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same dts is not available in Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> 
Update all A80 devicetree dtsi and dtsi files from
Linux-v4.18-rc3 with below commits.

arch/arm/boot/dts/sun9i-a80*:

commit 190e3138f9577885691540dca59c2f07540bde04
Merge: cafc87023b0d a7affb13b271
Author: Arnd Bergmann <arnd@arndb.de>
Date:   Tue Mar 27 14:58:00 2018 +0200

    Merge tag 'sunxi-h3-h5-for-4.17' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt

include/dt-bindings/*/sun9i-a80-*:

commit 783ab76ae553abc23f80ef7511052d055697531b
Author: Chen-Yu Tsai <wens@csie.org>
Date:   Sat Jan 28 20:22:36 2017 +0800

    clk: sunxi-ng: Add A80 Display Engine CCU

Note: sun9i-a80-cx-a99.dts is updated only uart0, since the same
dts is not available in Linux.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
reset: MedaiTek: add reset controller driver for MediaTek SoCs 2019-01-14T22:43:18+00:00 Weijie Gao weijie.gao@mediatek.com 2018-12-20T08:12:51+00:00 3e066bcaefb51adcf5c0594d42abe145f701dbeb This patch adds reset controller driver for MediaTek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 
This patch adds reset controller driver for MediaTek SoCs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
mips: jz47xx: Add JZ4780 SoC support 2018-12-19T14:23:01+00:00 Paul Burton paul.burton@imgtec.com 2018-12-16T22:25:22+00:00 cd71b1d5d26dfff15222f5df8a5a6df68fc41df7 Add initial support for the Ingenic JZ47xx MIPS SoC. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de> 
Add initial support for the Ingenic JZ47xx MIPS SoC.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
bmips: bcm6318: add support for bcm6368-enet 2018-12-19T14:23:01+00:00 Álvaro Fernández Rojas noltari@gmail.com 2018-12-01T18:00:41+00:00 93bd64bf0551e51d96cd25e107ca6589372d4377 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> 
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
bmips: bcm6318: add bcm6348-iudma support 2018-12-19T14:23:00+00:00 Álvaro Fernández Rojas noltari@gmail.com 2018-12-01T18:00:23+00:00 6e0faa22dd394d42221d4dc0ad2975466d08eb21 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> 
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>