u-boot.git/include/dt-bindings, branch v2021.01 Unnamed repository; edit this file 'description' to name the repository. imx: imx8mm: Update clock bindings header 2020-12-26T11:35:38+00:00 Adam Ford aford173@gmail.com 2020-12-04T23:27:45+00:00 d72cecec7fc0b04d6d52df44ae1e7033ee7e4099 Import clock bindings header file from Linux 5.10-rc6 Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Peng Fan <peng.fan@nxp.com> 
Import clock bindings header file from Linux 5.10-rc6

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
reset: stm32: Add support of MCU HOLD BOOT 2020-11-25T10:32:31+00:00 Patrick Delaunay patrick.delaunay@st.com 2020-10-15T13:01:11+00:00 d8d29a4489c72ed8cbeafa42ea5c06e26b80a2e5 Handle the register RCC_MP_GCR without SET/CLR registers but with a direct access to bit BOOT_MCU: - deassert => set the bit: The MCU will not be in HOLD_BOOT - assert => clear the bit: The MCU will be set in HOLD_BOOT With this patch the RCC driver handles the MCU_HOLD_BOOT_R value added in binding stm32mp1-resets.h Cc: Fabien DESSENNE <fabien.dessenne@st.com> Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> 
Handle the register RCC_MP_GCR without SET/CLR registers
but with a direct access to bit BOOT_MCU:
- deassert => set the bit: The MCU will not be in HOLD_BOOT
- assert => clear the bit: The MCU will be set in HOLD_BOOT

With this patch the RCC driver handles the MCU_HOLD_BOOT_R value
added in binding stm32mp1-resets.h

Cc: Fabien DESSENNE <fabien.dessenne@st.com>
Cc: Arnaud POULIQUEN <arnaud.pouliquen@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
sunxi: DT: A64: update device tree files 2020-11-17T00:42:20+00:00 Samuel Holland samuel@sholland.org 2020-10-24T15:21:55+00:00 e210ec0181ee5255ad3b2485a1b7bb7a9e50d55d Import updated device trees from Linux tag v5.9. This picks up new hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI files for the Pinebook and the Teres-I, since the ANX6345 bridge is now supported upstream. A couple of headers needed updates for recently-added hardware support. Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
Import updated device trees from Linux tag v5.9. This picks up new
hardware (PinePhone, PineTab); and it drops the U-Boot specific DTSI
files for the Pinebook and the Teres-I, since the ANX6345 bridge is
now supported upstream.

A couple of headers needed updates for recently-added hardware support.

Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Merge tag 'xilinx-for-v2021.01-v2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze 2020-10-29T15:30:15+00:00 Tom Rini trini@konsulko.com 2020-10-29T15:30:15+00:00 47754334b164eae4fde538c406ff3678dfb05042 Xilinx changes for v2021.01-v2 common: - Add support for 64bit loadables from SPL xilinx: - Update documentation and record ownership - Enable eeprom board detection based legacy and fru formats - Add support for FRU format microblaze: - Optimize low level ASM code - Enable SPI/I2C - Enable distro boot zynq: - Add support for Zturn V5 zynqmp: - Improve silicon detection code - Enable several kconfig options - Align DT with the latest state - Enabling security commands - Enable and support FPGA loading from SPL - Optimize xilinx_pm_request() calling versal: - Some DTs/Kconfig/defconfig alignments - Add binding header for clock and power zynq-sdhci: - Add support for tap delay programming zynq-spi/zynq-qspi: - Use clock framework for getting clocks xilinx-spi: - Fix some code issues (unused variables) serial: - Check return value from clock functions in pl01x 
Xilinx changes for v2021.01-v2

common:
- Add support for 64bit loadables from SPL

xilinx:
- Update documentation and record ownership
- Enable eeprom board detection based legacy and fru formats
- Add support for FRU format

microblaze:
- Optimize low level ASM code
- Enable SPI/I2C
- Enable distro boot

zynq:
- Add support for Zturn V5

zynqmp:
- Improve silicon detection code
- Enable several kconfig options
- Align DT with the latest state
- Enabling security commands
- Enable and support FPGA loading from SPL
- Optimize xilinx_pm_request() calling

versal:
- Some DTs/Kconfig/defconfig alignments
- Add binding header for clock and power

zynq-sdhci:
- Add support for tap delay programming

zynq-spi/zynq-qspi:
- Use clock framework for getting clocks

xilinx-spi:
- Fix some code issues (unused variables)

serial:
- Check return value from clock functions in pl01x
drivers: Add a new framework for multiplexer devices 2020-10-28T15:48:32+00:00 Jean-Jacques Hiblot jjhiblot@ti.com 2020-10-16T10:46:30+00:00 0ad40b2463053947da052e74be72938fa5e4735e Add a new subsystem that handles multiplexer controllers. The API is the same as in Linux. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Pratyush Yadav <p.yadav@ti.com> [trini: Update some error calls to use different functions or pass correct arguments] Signed-off-by: Tom Rini <trini@konsulko.com> 
Add a new subsystem that handles multiplexer controllers. The API is the
same as in Linux.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
[trini: Update some error calls to use different functions or pass
        correct arguments]
Signed-off-by: Tom Rini <trini@konsulko.com>
dt-bindings: arm64: versal: Add clk and power headers 2020-10-27T07:13:32+00:00 Michal Simek michal.simek@xilinx.com 2019-04-08T11:43:51+00:00 30f47c0f1bd84b9d46a3f99eca65f666991676a5 Add power and reset headers to be sources by Versal dtses. Signed-off-by: Michal Simek <michal.simek@xilinx.com> 
Add power and reset headers to be sources by Versal dtses.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
reset: ast2500: Use SCU for reset control 2020-10-22T15:26:14+00:00 Chia-Wei, Wang chiawei_wang@aspeedtech.com 2020-10-15T02:25:13+00:00 611a28ce271164941aac02feea19f1d87bd1cf32 The System Control Unit (SCU) controller of Aspeed SoCs provides the reset control for each peripheral. This patch refactors the reset method to leverage the SCU reset control. Thus the driver dependency on watchdog including dedicated WDT API and reset flag encoding can be eliminated. The Kconfig description is also updated accordingly. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com> 
The System Control Unit (SCU) controller of Aspeed
SoCs provides the reset control for each peripheral.

This patch refactors the reset method to leverage
the SCU reset control. Thus the driver dependency
on watchdog including dedicated WDT API and reset
flag encoding can be eliminated.

The Kconfig description is also updated accordingly.

Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
arm: dts: r8a774c0: Import DTS from Linux 5.9 2020-10-20T10:56:51+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2020-10-16T07:37:13+00:00 fc5e5522096af4917b189055dcd91e8d50c52149 Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9 commit bbf5c979011a ("Linux 5.9"). Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> 
Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
pinctrl: Add support for Kendryte K210 FPIOA 2020-10-08T15:42:36+00:00 Sean Anderson seanga2@gmail.com 2020-09-14T15:01:58+00:00 7224d5ccf8e1d2552e2994c5d55769c334231c08 The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
The Fully-Programmable Input/Output Array (FPIOA) device controls pin
multiplexing on the K210. The FPIOA can remap any supported function to any
multifunctional IO pin. It can also perform basic GPIO functions, such as
reading the current value of a pin. However, GPIO functionality remains
largely unimplemented (in favor of the dedicated GPIO peripherals).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
test: pinmux: Add test for pin muxing 2020-10-08T15:42:36+00:00 Sean Anderson seanga2@gmail.com 2020-09-14T15:01:57+00:00 7f0f1806e3a474dc15b6bad806b4afa967447774 This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> 
This extends the pinctrl-sandbox driver to support pin muxing, and adds a
test for that behaviour. The test is done in C and not python (like the
existing tests for the pinctrl uclass) because it needs to call
pinctrl_select_state.  Another option could be to add a command that
invokes pinctrl_select_state and then test everything in
test/py/tests/test_pinmux.py.

The pinctrl-sandbox driver now mimics the way that many pinmux devices
work.  There are two groups of pins which are muxed together, as well as
four pins which are muxed individually. I have tried to test all normal
paths. However, very few error cases are explicitly checked for.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>