u-boot.git/include/dt-bindings, branch v2023.07 Unnamed repository; edit this file 'description' to name the repository. arm: dts: imx93: sync device tree with Linux 2023-05-21T14:54:41+00:00 Peng Fan peng.fan@nxp.com 2023-04-28T04:08:37+00:00 596b9c4e1bbd119bfee0a3a2779ce79438d00d43 Sync device tree with next-20230426 Signed-off-by: Peng Fan <peng.fan@nxp.com> 
Sync device tree with next-20230426

Signed-off-by: Peng Fan <peng.fan@nxp.com>
ARM: dts: add devicetree for Renesas RZ/N1 SoC 2023-05-13T02:01:30+00:00 Ralph Siemsen ralph.siemsen@linaro.org 2023-05-13T01:36:54+00:00 4647a84b6c363271a9f67d20ec0b987b9d26b2b4 This is taken directly from Linux kernel 6.3 (commit 457391b0380335d5e9a5babdec90ac53928b23b4) Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> 
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
pinctrl: renesas: add R906G032 driver 2023-05-13T02:01:30+00:00 Ralph Siemsen ralph.siemsen@linaro.org 2023-05-13T01:36:52+00:00 e4aea57fa773ada9443176e2e39af0b4e1750c65 Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC. This is quite rudimentary right now, and only supports applying a default pin configuration as specified by the device tree. Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org> Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> 
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.

This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
dt-binding: histb-clock: add clocks definition for Hi3798MV200 2023-05-03T13:05:24+00:00 Yang Xiwen forbidden405@outlook.com 2023-04-01T11:17:35+00:00 08ad608aa22b13b42cfb1f32ce071e52791cd669 These clocks are found on Hi3798MV200 Signed-off-by: Yang Xiwen <forbidden405@outlook.com> 
These clocks are found on Hi3798MV200

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
arm: dts: Import device tree for Broadcom Northstar 2023-05-02T18:23:58+00:00 Linus Walleij linus.walleij@linaro.org 2023-04-24T07:38:28+00:00 8a5122bfd3bb8b60aba18788f1ce4d1d772c45a2 This brings in the main SoC device tree used by the Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x. This is taken from the v6.3 Linux kernel. Cc: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
This brings in the main SoC device tree used by the
Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
This is taken from the v6.3 Linux kernel.

Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dt-bindings: pinctrl: Add StarFive JH7110 pinctrl definitions 2023-04-20T08:08:44+00:00 Jianlong Huang jianlong.huang@starfivetech.com 2023-03-29T03:42:14+00:00 d60f38493837d70a66cb9655169459d65dbe5fca Add pinctrl definitions for StarFive JH7110 SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com> Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> 
Add pinctrl definitions for StarFive JH7110 SoC.

Signed-off-by: Kuan Lim Lee <kuanlim.lee@linux.starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: clock: Add StarFive JH7110 clock definitions 2023-04-20T08:08:44+00:00 Yanhong Wang yanhong.wang@starfivetech.com 2023-03-29T03:42:12+00:00 58c9c60b64a8d459ab0d204f9d5c468b0ae72e02 Add all clock outputs for the StarFive JH7110 clock generator. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Acked-by: Sean Anderson <seanga2@gmail.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> 
Add all clock outputs for the StarFive JH7110 clock generator.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: reset: Add StarFive JH7110 reset definitions 2023-04-20T08:08:44+00:00 Yanhong Wang yanhong.wang@starfivetech.com 2023-03-29T03:42:10+00:00 c10483045e2de75a16d88aea8cceee42c91056d7 Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and always-on(AON) reset controller. Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com> Tested-by: Conor Dooley <conor.dooley@microchip.com> 
Add resets for the StarFive JH7110 system(SYS),system-top-group(STG) and
always-on(AON) reset controller.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: clock: Add R8A779G0 V4H CPG Core Clock Definitions 2023-04-07T15:13:28+00:00 Tho Vu tho.vu.wh@renesas.com 2023-02-28T21:37:01+00:00 0296ec364dddc24bc956e5828b342257603c1a9e Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4H (R8A779G0) SoC from Linux next commit 058f4df42121 ("Add linux-next specific files for 20230228") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tho Vu <tho.vu.wh@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Update to linux next 20230228 state] 
Add all Clock Pulse Generator Core Clock Outputs for the
Renesas R-Car V4H (R8A779G0) SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update to linux next 20230228 state]
dt-bindings: power: Add R8A779G0 V4H SYSC power domain definitions 2023-04-07T15:13:28+00:00 Tho Vu tho.vu.wh@renesas.com 2023-02-28T21:37:00+00:00 3813c3c0a56da4093d4078191e15a48b8037b796 Add power domain indices for R-Car V4H (R8A779G0) from Linux next commit 058f4df42121 ("Add linux-next specific files for 20230228") Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tho Vu <tho.vu.wh@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> [Marek: Update to linux next 20230228 state] 
Add power domain indices for R-Car V4H (R8A779G0) from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Update to linux next 20230228 state]