u-boot.git/include/e500.h, branch v1.3.4 Unnamed repository; edit this file 'description' to name the repository. Reworked FSL Book-E TLB macros to be more readable 2008-01-09T22:25:03+00:00 Kumar Gala galak@kernel.crashing.org 2007-12-19T07:18:15+00:00 2146cf56821c3364786ca94a7306008c5824b238 The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
The old macros made it difficult to know what WIMGE and perm bits
were set for a TLB entry.  Actually use the bit masks for these items
since they are only a single bit.

Also moved the macros into mmu.h out of e500.h since they aren't specific
to e500.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use FSL Book-E MMU macros from Linux Kernel 2008-01-09T22:25:03+00:00 Kumar Gala galak@kernel.crashing.org 2007-12-19T05:21:51+00:00 1d47273d46925929f8f2c1913cd96d7257aade88 Grab the FSL Book-E MAS register macros from Linux. Also added defines for page sizes up to 4TB and removed SHAREN since it doesnt really exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
Grab the FSL Book-E MAS register macros from Linux.  Also added
defines for page sizes up to 4TB and removed SHAREN since it doesnt
really exist.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Handle Asynchronous DDR clock on 85xx 2007-12-12T04:34:20+00:00 Kumar Gala galak@kernel.crashing.org 2007-12-07T10:59:26+00:00 d435793229ce29a42797c1edc39f5b34f987f91a The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> 
The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.

Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Patch by Jon Loeliger, 16 Jul 2004: 2004-08-01T23:02:45+00:00 wdenk wdenk 2004-08-01T23:02:45+00:00 9aea95307fdb0ffe0d3a98a17ac73e5040c9756a - support larger DDR memories up to 2G on the PC8540/8560ADS and STXGP3 boards - Made MPC8540/8560ADS be 33Mhz PCI by default. - Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16 and CONFIG_L2_INIT_RAM options. - Refactor Local Bus initialization out of SDRAM setup. - Re-implement new version of LBC11/DDR11 errata workarounds. - Moved board specific PCI init parts out of CPU directory. - Added TLB entry for PCI-1 IO Memory - Updated README.mpc85xxads 
- support larger DDR memories up to 2G on the PC8540/8560ADS and
  STXGP3 boards
- Made MPC8540/8560ADS be 33Mhz PCI by default.
- Removed moldy CONFIG_RAM_AS_FLASH, CFG_FLASH_PORT_WIDTH_16
  and CONFIG_L2_INIT_RAM options.
- Refactor Local Bus initialization out of SDRAM setup.
- Re-implement new version of LBC11/DDR11 errata workarounds.
- Moved board specific PCI init parts out of CPU directory.
- Added TLB entry for PCI-1 IO Memory
- Updated README.mpc85xxads
* Patches by Xianghua Xiao, 15 Oct 2003: 2003-10-15T23:53:47+00:00 wdenk wdenk 2003-10-15T23:53:47+00:00 42d1f0394bef0624fc9664714d54bb137931d6a6 - Added Motorola CPU 8540/8560 support (cpu/85xx) - Added Motorola MPC8540ADS board support (board/mpc8540ads) - Added Motorola MPC8560ADS board support (board/mpc8560ads) * Minor code cleanup 
  - Added Motorola CPU 8540/8560 support (cpu/85xx)
  - Added Motorola MPC8540ADS board support (board/mpc8540ads)
  - Added Motorola MPC8560ADS board support (board/mpc8560ads)

* Minor code cleanup