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<title>u-boot.git/include/fpga.h, branch v2014.04</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
</subtitle>
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<entry>
<title>Add GPL-2.0+ SPDX-License-Identifier to source files</title>
<updated>2013-07-24T13:44:38+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2013-07-08T07:37:19+00:00</published>
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<id>1a4596601fd395f3afb8f82f3f840c5e00bdd57a</id>
<content type='text'>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
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<pre>
Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>fpga: Remove all CONFIG_SYS_* fpga related options</title>
<updated>2013-05-06T08:41:30+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2013-05-01T16:05:56+00:00</published>
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All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
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<pre>
All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>fpga: Check device name against bitstream name</title>
<updated>2013-05-06T08:41:25+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2013-04-26T13:04:48+00:00</published>
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<id>6631db4773cd735688bf3332173a49271df23385</id>
<content type='text'>
Ensure that wrong bitstream won't be loaded
to current device.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
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<pre>
Ensure that wrong bitstream won't be loaded
to current device.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>fpga: Change the first parameter in fpga_loadbitstream</title>
<updated>2013-05-06T08:41:20+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2013-05-01T17:02:02+00:00</published>
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<content type='text'>
All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
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<pre>
All fpga functions use devnum as int. Only fpga_loadbitstream
is using it as unsinged long dev.
This patch synchronize it.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>cmd: fpga: Move fpga_loadbitstream to fpga.c</title>
<updated>2013-05-06T08:41:19+00:00</updated>
<author>
<name>Michal Simek</name>
<email>michal.simek@xilinx.com</email>
</author>
<published>2013-04-26T11:12:07+00:00</published>
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<content type='text'>
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
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<pre>
In bitstream decoding you can directly check device
which you want to load and in fpga.c are fpga_validate
and fpga_dev_info functions which should be used for it.

Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Reviewed-by: Tom Rini &lt;trini@ti.com&gt;
</pre>
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</content>
</entry>
<entry>
<title>Consolidate bool type</title>
<updated>2013-04-01T20:33:52+00:00</updated>
<author>
<name>York Sun</name>
<email>yorksun@freescale.com</email>
</author>
<published>2013-04-01T18:29:11+00:00</published>
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<id>472d546054dadacca91530bad42ad06f6408124e</id>
<content type='text'>
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
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<pre>
'bool' is defined in random places. This patch consolidates them into a
single header file include/linux/types.h, using stdbool.h introduced in C99.

All other #define, typedef and enum are removed. They are all consistent with
true = 1, false = 0.

Replace FALSE, False with false. Replace TRUE, True with true.
Skip *.py, *.php, lib/* files.

Signed-off-by: York Sun &lt;yorksun@freescale.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fpga: constify to fix build warning</title>
<updated>2011-08-01T13:19:40+00:00</updated>
<author>
<name>Wolfgang Denk</name>
<email>wd@denx.de</email>
</author>
<published>2011-07-30T13:33:49+00:00</published>
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<id>e6a857da746d5d7d450e59c0f86664c6b279b1c2</id>
<content type='text'>
Fix compiler warning:

cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type

Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Andre Schwarz &lt;andre.schwarz@matrix-vision.de&gt;
Cc: Murray Jensen &lt;Murray.Jensen@csiro.au&gt;
Acked-by: Andre Schwarz&lt;andre.schwarz@matrix-vision.de&gt;
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<pre>
Fix compiler warning:

cmd_fpga.c:318: warning: passing argument 3 of 'fit_image_get_data'
from incompatible pointer type

Adding the needed 'const' here entails a whole bunch of additonal
changes all over the FPGA code.

Signed-off-by: Wolfgang Denk &lt;wd@denx.de&gt;
Cc: Andre Schwarz &lt;andre.schwarz@matrix-vision.de&gt;
Cc: Murray Jensen &lt;Murray.Jensen@csiro.au&gt;
Acked-by: Andre Schwarz&lt;andre.schwarz@matrix-vision.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>FPGA: add support for downloading Lattice bitstream</title>
<updated>2010-10-13T16:09:31+00:00</updated>
<author>
<name>Stefano Babic</name>
<email>sbabic@denx.de</email>
</author>
<published>2010-06-29T09:47:48+00:00</published>
<link rel='alternate' type='text/html' href='http://cgit.235523.xyz/u-boot.git/commit/?id=3b8ac464f25581a7d22b303a9154c05e0c7f40a8'/>
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<content type='text'>
The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.

The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
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<pre>
The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.

The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.

Signed-off-by: Stefano Babic &lt;sbabic@denx.de&gt;
</pre>
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</content>
</entry>
<entry>
<title>fpga: Remove relocation fixups</title>
<updated>2009-10-03T08:17:56+00:00</updated>
<author>
<name>Peter Tyser</name>
<email>ptyser@xes-inc.com</email>
</author>
<published>2009-09-21T16:20:32+00:00</published>
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<content type='text'>
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups.  Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
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<pre>
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups.  Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.

Signed-off-by: Peter Tyser &lt;ptyser@xes-inc.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>rename CFG_ macros to CONFIG_SYS</title>
<updated>2008-10-18T19:54:03+00:00</updated>
<author>
<name>Jean-Christophe PLAGNIOL-VILLARD</name>
<email>plagnioj@jcrosoft.com</email>
</author>
<published>2008-10-16T13:01:15+00:00</published>
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<content type='text'>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
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<pre>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD &lt;plagnioj@jcrosoft.com&gt;
</pre>
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