u-boot.git/include/fsl_ddr.h, branch v2016.09

Add more SPDX-License-Identifier tags

2016-01-19T13:31:21+00:00

In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini

drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

2015-11-30T17:11:11+00:00

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun

drivers/ddr/fsl: Adjust bstopre value

2015-08-03T19:06:38+00:00

By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.

Signed-off-by: York Sun

driver/ddr/fsl: Add a hook to update SPD address

2015-07-20T18:44:35+00:00

In case SPD address changes between board revisions, updating SPD
address can be called from board file.

Signed-off-by: York Sun 
Signed-off-by: Prabhakar Kushwaha

drivers/ddr/fsl: Update DDR driver for DDR4

2015-04-23T15:55:53+00:00

Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.

Signed-off-by: York Sun

driver/ddr/fsl: Add sync of refresh

2015-02-24T21:09:42+00:00

Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.

Signed-off-by: York Sun

driver/ddr/fsl: Add support for multiple DDR clocks

2015-02-24T21:09:18+00:00

Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.

Signed-off-by: York Sun

arm/ls1021a: Add workaround for DDR erratum A008378

2015-01-24T04:29:13+00:00

Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

Signed-off-by: York Sun

driver/ddr: Restruct driver to allow standalone memory space

2014-09-25T15:36:18+00:00

U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.

Signed-off-by: York Sun

driver/ddr/fsl: Add DDR4 support to Freescale DDR driver

2014-04-23T00:58:48+00:00

Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun