u-boot.git/include/kendryte/pll.h, branch master

k210: use the board vendor name rather than the marketing name

2022-03-15T09:43:11+00:00

"kendryte" is the marketing name for the K210 RISC-V SoC produced by
Canaan Inc. Rather than "kendryte,k210", use the usual "canaan,k210"
vendor,SoC compatibility string format in the device tree files and
use the SoC name for file names.
With these changes, the device tree files are more in sync with the
Linux kernel DTS and drivers, making uboot device tree usable by the
kernel.

Signed-off-by: Damien Le Moal 
Signed-off-by: Niklas Cassel 
Reviewed-by: Leo Yu-Chi Liang

clk: k210: Move pll into the rest of the driver

2021-06-17T01:40:57+00:00

Now that there no separate PLL driver, we can no longer make the PLL
functions static. By moving the PLL driver in with the rest of the clock
code, we can make these functions static again. We still keep the pll
header for unit testing, but it is pretty reduced.

Signed-off-by: Sean Anderson 
Reviewed-by: Leo Yu-Chi Liang

clk: k210: Rewrite to remove CCF

2021-06-17T01:40:57+00:00

This is effectively a complete rewrite to remove all dependency on CCF.
The code is now smaller, and so is the binary. It also takes up less memory
at runtime (since we don't have to create 40 udevices). In general, I am
much happier with this driver as much of the complexity and late binding
has been removed.

The k210_*_params structs which were previously used to initialize CCF
clocks are now used as the complete configuration. Since we can write our
own division logic, we can now do away with several "half" clocks which
only existed to provide constant factors of two.

The clock IDs have been renumbered to remove unused clocks. This may not be
the last time they are renumbered, since we have diverged with Linux. There
are also still a few clocks left out which may need to be added back in.

In general, I have tried to leave out behavioral changes. However, there is
a small bugfix regarding ACLK. According to the technical reference manual,
its mux comes *after* its divider (which is present only for PLL0). This
would have required yet another intermediate clock to fix with CCF, but
with the new driver it is just 2 lines of code :)

Signed-off-by: Sean Anderson 
Reviewed-by: Leo Yu-Chi Liang

clk: k210: Remove k210_register_pll

2021-05-14T08:20:48+00:00

This simplifies the PLL creation process, since we don't have to pass all
the parameters individually.

Signed-off-by: Sean Anderson

clk: kendryte/pll.h: do not redefine nop()

2020-08-25T01:33:35+00:00

The kendryte PLL code uses nop as barrier. The macro is not defined for
the sandbox on x86 but is defined on RISC-V.

Signed-off-by: Heinrich Schuchardt 
Reviewed-by: Sean Anderson 
Reviewed-by: Bin Meng

clk: Add K210 pll support

2020-07-01T07:01:21+00:00

This pll code is primarily based on the code from the kendryte standalone
sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to
the algorithm used to set the pll frequency, but it has been completely
rewritten to be fixed-point based.

Signed-off-by: Sean Anderson 
CC: Lukasz Majewski