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<title>u-boot.git/include/linux/clk, branch v2021.07-rc3</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.</subtitle>
<id>http://cgit.235523.xyz/u-boot.git/atom/include/linux/clk?h=v2021.07-rc3</id>
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<updated>2020-09-22T08:27:18Z</updated>
<entry>
<title>clk: at91: add pre-requisite headers for AT91 clock architecture</title>
<updated>2020-09-22T08:27:18Z</updated>
<author>
<name>Claudiu Beznea</name>
<email>claudiu.beznea@microchip.com</email>
</author>
<published>2020-09-07T14:46:37Z</published>
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<id>urn:sha1:643966a8fa620b763ad2c20c4d328aaefa23901d</id>
<content type='text'>
Add pre-requisite headers for AT91 clock architecture. These
are based on already present files on Linux and will be used
by following commits for AT91 CCF clock drivers.

Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
</content>
</entry>
<entry>
<title>clk: sifive: Sync-up WRPLL library with upstream Linux</title>
<updated>2019-07-19T06:24:51Z</updated>
<author>
<name>Anup Patel</name>
<email>Anup.Patel@wdc.com</email>
</author>
<published>2019-06-25T06:31:08Z</published>
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<id>urn:sha1:c236802696ec2ad3b9110d7db9e601c27e61e8bc</id>
<content type='text'>
Now that SiFive clock driver is merged in upstream Linux, we
sync-up WRPLL library used by SiFive clock driver with upstream
Linux sources.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>clk: sifive: Factor-out PLL library as separate module</title>
<updated>2019-07-19T06:24:51Z</updated>
<author>
<name>Anup Patel</name>
<email>Anup.Patel@wdc.com</email>
</author>
<published>2019-06-25T06:31:02Z</published>
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<id>urn:sha1:d04c79d2b238e857c1b1f45a78d173152792b371</id>
<content type='text'>
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
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