u-boot.git/include/linux/clk, branch v2023.01-rc2 Unnamed repository; edit this file 'description' to name the repository. clk: at91: add pre-requisite headers for AT91 clock architecture 2020-09-22T08:27:18+00:00 Claudiu Beznea claudiu.beznea@microchip.com 2020-09-07T14:46:37+00:00 643966a8fa620b763ad2c20c4d328aaefa23901d Add pre-requisite headers for AT91 clock architecture. These are based on already present files on Linux and will be used by following commits for AT91 CCF clock drivers. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> 
Add pre-requisite headers for AT91 clock architecture. These
are based on already present files on Linux and will be used
by following commits for AT91 CCF clock drivers.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
clk: sifive: Sync-up WRPLL library with upstream Linux 2019-07-19T06:24:51+00:00 Anup Patel Anup.Patel@wdc.com 2019-06-25T06:31:08+00:00 c236802696ec2ad3b9110d7db9e601c27e61e8bc Now that SiFive clock driver is merged in upstream Linux, we sync-up WRPLL library used by SiFive clock driver with upstream Linux sources. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
Now that SiFive clock driver is merged in upstream Linux, we
sync-up WRPLL library used by SiFive clock driver with upstream
Linux sources.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
clk: sifive: Factor-out PLL library as separate module 2019-07-19T06:24:51+00:00 Anup Patel Anup.Patel@wdc.com 2019-06-25T06:31:02+00:00 d04c79d2b238e857c1b1f45a78d173152792b371 To match SiFive clock driver with latest Linux, we factor-out PLL library as separate module under drivers/clk/analogbits. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
To match SiFive clock driver with latest Linux, we factor-out PLL
library as separate module under drivers/clk/analogbits.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>