u-boot.git/include/linux/intel-smc.h, branch next Unnamed repository; edit this file 'description' to name the repository. arm: socfpga: soc64: Update reset manager registers for F2S bridge 2025-04-22T03:47:39+00:00 Alif Zakuan Yuslaimi alif.zakuan.yuslaimi@altera.com 2025-04-04T02:07:02+00:00 9acad2b4c7214bb423a6221b67b0d7ea37edbdf7 Add reset manager registers in preparation for F2S bridge reset support as well as the mask support to enable/disable the bridges. Mask value: BIT0: soc2fpga BIT1: lwhps2fpga BIT2: fpga2soc These bridges are available only in Stratix10: BIT3: f2sdram0 BIT4: f2sdram1 BIT5: f2sdram2 Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> 
Add reset manager registers in preparation for F2S bridge reset
support as well as the mask support to enable/disable the bridges.

Mask value:
BIT0: soc2fpga
BIT1: lwhps2fpga
BIT2: fpga2soc

These bridges are available only in Stratix10:
BIT3: f2sdram0
BIT4: f2sdram1
BIT5: f2sdram2

Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
arm: socfpga: smc: Add function to get usercode 2021-04-08T09:29:13+00:00 Siew Chin Lim elly.siew.chin.lim@intel.com 2021-03-25T06:07:45+00:00 96fe4f6485e92ed9da464c96c5f536698c5ee66d Add function to send mailbox command via SMC to get usercode from SDM. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> 
Add function to send mailbox command via SMC to get usercode from SDM.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
arm: socfpga: smc: Remove unused SMC function ID 2021-04-08T09:29:11+00:00 Siew Chin Lim elly.siew.chin.lim@intel.com 2021-03-12T09:51:10+00:00 4e521e143082db6821bd3ee36f5cb990d8105253 Remove unused SMC function ID 61 and 62. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com> 
Remove unused SMC function ID 61 and 62.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services 2021-01-15T09:48:36+00:00 Chee Hong Ang chee.hong.ang@intel.com 2020-12-24T10:21:01+00:00 313de7335248ff3246e4f2da4e63e50c350a2ac3 This header file defines the Secure Monitor Call (SMC) message protocol for ATF (BL31) PSCI runtime services. It includes all the PSCI SiP function identifiers for the secure runtime services provided by ATF. The secure runtime services include System Manager's registers access, 2nd phase bitstream FPGA reconfiguration, Remote System Update (RSU) and etc. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> 
This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers access, 2nd phase bitstream FPGA reconfiguration, Remote
System Update (RSU) and etc.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>