u-boot.git/include/linux/mtd/spinand.h, branch v2023.04 Unnamed repository; edit this file 'description' to name the repository. spi: Tidy up get/set of device node 2021-01-05T19:24:41+00:00 Simon Glass sjg@chromium.org 2020-12-19T17:40:00+00:00 e2a7cfe9d5fce65789972a31ff50fb1d8d509848 This code is a bit odd in that it only reads and updates the livetree version of the device ofnode. This means it won't work with flattree. Update the code to work as it was presumably intended. Signed-off-by: Simon Glass <sjg@chromium.org> 
This code is a bit odd in that it only reads and updates the livetree
version of the device ofnode. This means it won't work with flattree.
Update the code to work as it was presumably intended.

Signed-off-by: Simon Glass <sjg@chromium.org>
mtd: spinand: micron: identify SPI NAND device with Continuous Read mode 2020-07-20T16:58:33+00:00 Shivamurthy Shastri sshivamurthy@micron.com 2020-07-07T20:04:11+00:00 720fcb27e0be500a718fffd9c1910f8ed94e7745 Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> 
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.

Hence, we disable the feature at probe time.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: spi-nand: Import Toshiba SPI-NAND support 2020-04-28T20:14:35+00:00 Robert Marko robert.marko@sartura.hr 2020-03-03T19:25:40+00:00 89127104848cea38bac5d40e3d6973fc203e2df6 Linux has good support for Toshiba SPI-NAND, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Tested-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
Linux has good support for Toshiba SPI-NAND, so lets import it.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Tested-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: nand: spi: Add Gigadevice SPI NAND support 2018-10-04T12:54:24+00:00 Stefan Roese sr@denx.de 2018-08-16T16:05:08+00:00 9e5c2a755a6ca5f3931de548f43101d0d18ac003 This patch adds support for Gigadevices SPI NAND device to the new SPI NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC device is supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Boris Brezillon <boris.brezillon@bootlin.com> Cc: Jagan Teki <jagan@openedev.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> 
This patch adds support for Gigadevices SPI NAND device to the new SPI
NAND infrastructure in U-Boot. Currently only the 128MiB GD5F1GQ4UC
device is supported.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Boris Brezillon <boris.brezillon@bootlin.com>
Cc: Jagan Teki <jagan@openedev.com>
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
mtd: spinand: Add initial support for the MX35LF1GE4AB chip 2018-09-20T14:40:49+00:00 Boris Brezillon boris.brezillon@bootlin.com 2018-08-16T15:30:15+00:00 6f041ccabb03bea16c2f21f3254dc9c1cb38425c Add minimal support for the MX35LF1GE4AB SPI NAND chip. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> 
Add minimal support for the MX35LF1GE4AB SPI NAND chip.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
mtd: spinand: Add initial support for Winbond W25M02GV 2018-09-20T14:40:49+00:00 Frieder Schrempf frieder.schrempf@exceet.de 2018-08-16T15:30:14+00:00 3181c0a622d35bd8e6d4407458e7204d4df5a8c1 Add support for the W25M02GV chip. Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> 
Add support for the W25M02GV chip.

Signed-off-by: Frieder Schrempf <frieder.schrempf@exceet.de>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
mtd: spinand: Add initial support for Micron MT29F2G01ABAGD 2018-09-20T14:40:49+00:00 Peter Pan peterpandong@micron.com 2018-08-16T15:30:13+00:00 883d8778ae177172c0a53c018faa39e61f30dea3 Add a basic driver for Micron SPI NANDs. Only one device is supported right now, but the driver will be extended to support more devices afterwards. Signed-off-by: Peter Pan <peterpandong@micron.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> 
Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more devices
afterwards.

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
mtd: nand: Add core infrastructure to support SPI NANDs 2018-09-20T14:40:49+00:00 Peter Pan peterpandong@micron.com 2018-08-16T15:30:12+00:00 0a6d6bae03864938f073cc114992c40f2338a155 Add a SPI NAND framework based on the generic NAND framework and the spi-mem infrastructure. In its current state, this framework supports the following features: - single/dual/quad IO modes - on-die ECC Signed-off-by: Peter Pan <peterpandong@micron.com> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> 
Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.

In its current state, this framework supports the following features:

- single/dual/quad IO modes
- on-die ECC

Signed-off-by: Peter Pan <peterpandong@micron.com>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>