u-boot.git/include/linux/mtd, branch v2020.10-rc5 Unnamed repository; edit this file 'description' to name the repository. mtd: spinand: micron: identify SPI NAND device with Continuous Read mode 2020-07-20T16:58:33+00:00 Shivamurthy Shastri sshivamurthy@micron.com 2020-07-07T20:04:11+00:00 720fcb27e0be500a718fffd9c1910f8ed94e7745 Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com> 
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.

Hence, we disable the feature at probe time.

Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
arm: Don't include common.h in header files 2020-05-18T18:54:24+00:00 Simon Glass sjg@chromium.org 2020-05-10T17:39:55+00:00 c3dc39a2f85b16bf590789f7e283cd72275cd168 It is bad practice to include common.h in other header files since it can bring in any number of superfluous definitions. It implies that some C files don't include it and thus may be missing CONFIG options that are set up by that file. The C files should include these themselves. Update some header files in arch/arm to drop this. Signed-off-by: Simon Glass <sjg@chromium.org> 
It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.

Update some header files in arch/arm to drop this.

Signed-off-by: Simon Glass <sjg@chromium.org>
mtd: spi-nor: Enable QE bit for ISSI flash 2020-04-30T17:04:20+00:00 Jagan Teki jagan@amarulasolutions.com 2020-04-20T10:06:06+00:00 5bf3f3dd11db4048d7ad60f2ee210dc50da26051 Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> 
Enable QE bit for ISSI flash chips.

QE enablement logic is similar to what Macronix
has, so reuse the existing code itself.

Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: spi-nand: Import Toshiba SPI-NAND support 2020-04-28T20:14:35+00:00 Robert Marko robert.marko@sartura.hr 2020-03-03T19:25:40+00:00 89127104848cea38bac5d40e3d6973fc203e2df6 Linux has good support for Toshiba SPI-NAND, so lets import it. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Tested-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
Linux has good support for Toshiba SPI-NAND, so lets import it.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Tested-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: Rename free() to rfree() 2020-02-06T02:33:46+00:00 Simon Glass sjg@chromium.org 2020-02-03T14:35:56+00:00 8d38a8459b0de45f5ff41f3e11c278a5cf395fd0 This function name conflicts with our desire to #define free() to something else on sandbox. Since it deals with resources, rename it to rfree(). Signed-off-by: Simon Glass <sjg@chromium.org> 
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().

Signed-off-by: Simon Glass <sjg@chromium.org>
mtd: spi-nor-core: Add octal mode support 2020-01-27T16:57:22+00:00 Vignesh Raghavendra vigneshr@ti.com 2019-12-05T10:16:05+00:00 658df8bd946493e7fa7b0048a3a9bd658a1f4518 Add support for Octal flash devices. Octal flash devices use 8 IO lines for data transfer. Currently only 1-1-8 Octal Read mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
Add support for Octal flash devices. Octal flash devices use 8 IO lines
for data transfer. Currently only 1-1-8 Octal Read mode is supported.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: spi: spi-nor-core: Add SST vendor specific SFDP parser 2019-12-17T07:49:05+00:00 Tudor Ambarus tudor.ambarus@microchip.com 2019-11-13T15:42:52+00:00 a11c081da3dfbef309cd21ab54b7b2582d0c9f35 JESD216 allow vendors to define their own SFDP tables. Add SST SFDP parser. The vendor table is allocated using resource-managed kmalloc - the table will be freed on driver detach. It will be accessible by getting the UCLASS_SPI_FLASH's private data. The SST's SFDP table is particularly of interest because contains pre-programmed globally unique EUI-48 and EUI-64 identifiers. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> 
JESD216 allow vendors to define their own SFDP tables.

Add SST SFDP parser. The vendor table is allocated using resource-managed
kmalloc - the table will be freed on driver detach. It will be accessible
by getting the UCLASS_SPI_FLASH's private data.

The SST's SFDP table is particularly of interest because contains
pre-programmed globally unique EUI-48 and EUI-64 identifiers.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
cmd: nand/sf: isolate legacy code 2019-12-04T22:10:51+00:00 Miquel Raynal miquel.raynal@bootlin.com 2019-10-25T17:39:29+00:00 eb446ef625bcff969f3e1d3a6874ce9d56113e9b The 'sf' command is not supposed to rely on the MTD stack, but both 'sf' and 'nand' commands use helpers located in mtd_uboot.c. Despite their location, these functions do not depend at all on the MTD stack. This file (drivers/mtd/mtd_uboot.c) is only compiled if CONFIG_MTD is selected, which is inconsistent with the current situation. Solve this by moving these three functions (which are only used by the above two commands) out of mtd_uboot.c and put them in a C file only compiled with cmd/sf.c and cmd/nand.c. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> [trini: Don't export get_part function now] Signed-off-by: Tom Rini <trini@konsulko.com> 
The 'sf' command is not supposed to rely on the MTD stack, but both
'sf' and 'nand' commands use helpers located in mtd_uboot.c. Despite
their location, these functions do not depend at all on the MTD
stack.

This file (drivers/mtd/mtd_uboot.c) is only compiled if CONFIG_MTD is
selected, which is inconsistent with the current situation. Solve this
by moving these three functions (which are only used by the above two
commands) out of mtd_uboot.c and put them in a C file only compiled
with cmd/sf.c and cmd/nand.c.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
[trini: Don't export get_part function now]
Signed-off-by: Tom Rini <trini@konsulko.com>
mtd: spi: Add 'struct spi_flash {' to the code 2019-10-08T05:51:00+00:00 Simon Glass sjg@chromium.org 2019-09-25T14:11:13+00:00 7e45bb0867fd88ff044a71903882e6ff098dea11 At present spi_flash is defined to be spi_nor which is confusing since it is not possible to find the 'spi_flash' by normal text search. Add a comment to help with this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> 
At present spi_flash is defined to be spi_nor which is confusing since it
is not possible to find the 'spi_flash' by normal text search. Add a
comment to help with this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
mtd: spi-nor: add missing SST26* flash IC protection ops 2019-09-16T02:39:22+00:00 Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com 2019-09-09T19:33:14+00:00 e0cacdcc0a479dc70d3048ee40705478dce2655e Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework) performs switch from previous 'spi_flash' infrastructure without proper testing/investigations which results in a regressions for SST26 flash series. Add missing SST26* flash IC protection ops which were introduced previously by Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs protection ops) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
Commit c4e8862308d4 (mtd: spi: Switch to new SPI NOR framework)
performs switch from previous 'spi_flash' infrastructure without
proper testing/investigations which results in a regressions for
SST26 flash series.

Add missing SST26* flash IC protection ops which were introduced
previously by
Commit 3d4fed87a5fa (mtd: sf: Add support of sst26wf* flash ICs
protection ops)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>