u-boot.git/include/linux/mtd, branch v2023.07-rc5 Unnamed repository; edit this file 'description' to name the repository. mtd: Drop unused fsmc_nand driver 2023-02-07T19:33:49+00:00 Simon Glass sjg@chromium.org 2023-02-01T20:19:49+00:00 6a138b0be30597a2d94001b96278885702ab931d This is not used since this commit: 570c3dcfc15 arm: Remove spear600 boards and the rest of SPEAr support Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> 
This is not used since this commit:

   570c3dcfc15 arm: Remove spear600 boards and the rest of SPEAr support

Drop the driver and Kconfig option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
mtd: Drop unused fsl_upm driver 2023-02-07T19:33:48+00:00 Simon Glass sjg@chromium.org 2023-02-01T20:19:48+00:00 2661c2da6d929cb64f9798a8d8cc03bc86c09b4a This is not used since this commit: 8d1e3cb1400 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support Drop the driver and Kconfig option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com> 
This is not used since this commit:

   8d1e3cb1400 powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS support

Drop the driver and Kconfig option.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
mtd: spi-nor: Add support for Infineon s25fs256t 2023-01-26T15:37:45+00:00 Takahiro Kuwano Takahiro.Kuwano@infineon.com 2022-12-19T01:28:21+00:00 87a6d86571268be4e354fe030c53745a54f4ed8e Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and differences comparing to other Spansion/Cypress flash familes are: - 4-byte address mode by factory default - Quad mode is enabled by factory default - Supports mixture of 128KB and 64KB sectors by OTP configuration (this patch supports uniform 128KB only) Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
Infineon S25FS256T is 256Mbit Quad SPI NOR flash. The key features and
differences comparing to other Spansion/Cypress flash familes are:
  - 4-byte address mode by factory default
  - Quad mode is enabled by factory default
  - Supports mixture of 128KB and 64KB sectors by OTP configuration
    (this patch supports uniform 128KB only)

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: spi-nor-core: Make CFRx reg fields generic 2023-01-26T15:28:09+00:00 Takahiro Kuwano Takahiro.Kuwano@infineon.com 2023-01-20T03:28:22+00:00 da16d72efd004e046b8b4f98a662afd4bef09206 Cypress defines two flavors of configuration registers, volatile and non volatile, and both use the same bit fields. Rename the bitfields in the configuration registers so that they can be used for both flavors. Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
Cypress defines two flavors of configuration registers, volatile and
non volatile, and both use the same bit fields. Rename the bitfields in
the configuration registers so that they can be used for both flavors.

Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: spi-nor-core: Consider reserved bits in CFR5 register 2023-01-26T15:27:39+00:00 Takahiro Kuwano Takahiro.Kuwano@infineon.com 2023-01-20T03:28:21+00:00 ee7296bbcd6bae3ded087cb56c786da10aa6fc6a CFR5[6] is reserved bit and must be always 1. Set it to comply with flash requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition, stop using magic numbers and describe the missing bit fields in CFR5 register. This is useful for both readability and future possible addition of Octal STR mode support. Fixes: ea9a22f7e79c ("mtd: spi-nor-core: Add support for Cypress Semper flash") Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Dhruva Gole <d-gole@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
CFR5[6] is reserved bit and must be always 1. Set it to comply with flash
requirements. While fixing SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN definition,
stop using magic numbers and describe the missing bit fields in CFR5
register. This is useful for both readability and future possible addition
of Octal STR mode support.

Fixes: ea9a22f7e79c ("mtd: spi-nor-core: Add support for Cypress Semper flash")
Suggested-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: rawnand: omap_elm: u-boot driver model support 2023-01-08T09:38:50+00:00 Roger Quadros rogerq@kernel.org 2022-12-20T10:22:03+00:00 7363cf0581a3e70b3dbd346dec8b7ae652776f80 Support u-boot driver model. We still retain support legacy way of doing things if ELM_BASE is defined in <asm/arch/hardware.h> We could completely get rid of that if all platforms defining ELM_BASE get rid of that definition and enable CONFIG_SYS_NAND_SELF_INIT and are verified to work. Signed-off-by: Roger Quadros <rogerq@kernel.org> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Tom Rini <trini@konsulko.com> Link: https://lore.kernel.org/all/20221220102203.52398-9-rogerq@kernel.org Link: https://lore.kernel.org/all/CABGWkvrvKiVA_yaDnHJcHEKwc+pEuLdz=i6HQEY0oJQvohCUsw@mail.gmail.com 
Support u-boot driver model. We still retain
support legacy way of doing things if ELM_BASE
is defined in <asm/arch/hardware.h>

We could completely get rid of that if all
platforms defining ELM_BASE get rid of that definition
and enable CONFIG_SYS_NAND_SELF_INIT and are verified
to work.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/all/20221220102203.52398-9-rogerq@kernel.org
Link: https://lore.kernel.org/all/CABGWkvrvKiVA_yaDnHJcHEKwc+pEuLdz=i6HQEY0oJQvohCUsw@mail.gmail.com
mtd: nand: drop EXPORT_SYMBOL_GPL for nanddev_erase() 2022-12-10T13:35:55+00:00 Dario Binacchi dario.binacchi@amarulasolutions.com 2022-11-08T09:07:19+00:00 670789f5ba2f3330b137f637deb47671b8720c33 This function is only used within this module, so it is no longer necessary to use EXPORT_SYMBOL_GPL(). This patch parallels the work done in the following patch: https://lore.kernel.org/linux-mtd/20221018170205.1733958-1-dario.binacchi@amarulasolutions.com Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com> Link: https://lore.kernel.org/all/20221108090719.3631621-1-dario.binacchi@amarulasolutions.com 
This function is only used within this module, so it is no longer
necessary to use EXPORT_SYMBOL_GPL().

This patch parallels the work done in the following patch:
https://lore.kernel.org/linux-mtd/20221018170205.1733958-1-dario.binacchi@amarulasolutions.com

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-By: Michael Trimarchi <michael@amarulasolutions.com>
Link: https://lore.kernel.org/all/20221108090719.3631621-1-dario.binacchi@amarulasolutions.com
memory: Add TI GPMC driver 2022-10-26T19:21:12+00:00 Roger Quadros rogerq@kernel.org 2022-10-20T13:30:49+00:00 9b0b5648d6e4d89aa594022e48894e811c250d5f The GPMC is a unified memory controller dedicated for interfacing with external memory devices like - Asynchronous SRAM-like memories and ASICs - Asynchronous, synchronous, and page mode burst NOR flash - NAND flash - Pseudo-SRAM devices This driver will take care of setting up the GPMC based on the settings specified in the Device tree and then probe its children. Signed-off-by: Roger Quadros <rogerq@kernel.org> 
The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
 - Asynchronous SRAM-like memories and ASICs
 - Asynchronous, synchronous, and page mode burst NOR flash
 - NAND flash
 - Pseudo-SRAM devices

This driver will take care of setting up the GPMC based on
the settings specified in the Device tree and then
probe its children.

Signed-off-by: Roger Quadros <rogerq@kernel.org>
mtd: spi-nor-core: Track flash's internal address mode 2022-10-23T05:20:17+00:00 Takahiro Kuwano Takahiro.Kuwano@infineon.com 2022-09-01T06:05:31+00:00 4d60001fdf0c13ab1ccf720bb3cd6e5d385386bb The nor->addr_width tracks number of address bytes used in read/program/erase ops and eventually set to 4 for >16MB chips, regardless of flash's internal address mode. For Infineon SEMPER flash's, we use Read/Write Any Register commands for configuration and status check. These commands take 3- or 4-byte address depending on flash's internal address mode. Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> 
The nor->addr_width tracks number of address bytes used in
read/program/erase ops and eventually set to 4 for >16MB chips, regardless
of flash's internal address mode. For Infineon SEMPER flash's, we use
Read/Write Any Register commands for configuration and status check.
These commands take 3- or 4-byte address depending on flash's internal
address mode.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
mtd: Update the function name to 'rfree' 2022-10-09T08:42:26+00:00 Fabio Estevam festevam@denx.de 2022-10-07T14:35:53+00:00 7676811867b54d4cb7b3356505d41511614884f3 Since commit 8d38a8459b0d ("mtd: Rename free() to rfree()") the function has been renamed to rfree(), so update the description inside the mtd_oob_region structure as well. Fixes: 8d38a8459b0d ("mtd: Rename free() to rfree()") Reported-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Signed-off-by: Fabio Estevam <festevam@denx.de> Acked-by: Michael Trimarchi <michael@amarulasolutions.com> Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> 
Since commit 8d38a8459b0d ("mtd: Rename free() to rfree()")
the function has been renamed to rfree(), so update the description
inside the mtd_oob_region structure as well.

Fixes: 8d38a8459b0d ("mtd: Rename free() to rfree()")
Reported-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>