u-boot.git/include/linux, branch v2014.10-rc1

kconfig: import Kconfig files from Linux 3.16-rc7

2014-07-30T12:47:46+00:00

Import
  - scripts/kconfig/*
  - include/linux/kconfig.h
from Linux 3.16-rc7.

Signed-off-by: Masahiro Yamada 
Reviewed-by: Simon Glass

qe: move immap_qe.h from arch directory into common directory

2014-07-22T23:25:54+00:00

ls1021 is arm-core and supports qe too.
Move immap_qe.h into common directory for both arm and powerpc.

Signed-off-by: Zhao Qiang 
Reviewed-by: York Sun

linux/compat.h: port lower_32_bits and upper_32_bits from Linux

2014-07-22T11:44:24+00:00

[backport from linux commit 204b885e and 218e180e7]
64 bit processors are becomming more and more popular.
lower_32_bits and upper_32_bits save our labor doing
shifts/manipulations like (u32)(n) and (u32)((n) >> 32).
They are good helpers in both little and big endian cases.
Port these two functions here from Linux:include/linux/kernel.h,
cater the comment message to little/big endian cases.
Later on, developers could include linux/compat.h if they want to
use these two functions.

Signed-off-by: Lijun Pan

mtd: nand: omap: add support for BCH16_ECC - NAND driver updates

2014-06-06T21:46:10+00:00

This patch add support for BCH16_ECC to omap_gpmc driver.

*need to BCH16 ECC scheme*
With newer SLC Flash technologies and MLC NAND, and large densities, pagesizes
Flash devices have become more suspectible to bit-flips. Thus stronger
ECC schemes are required for protecting the data.
But stronger ECC schemes have come with larger-sized ECC syndromes which require
more space in OOB/Spare. This puts constrains like;
(a) BCH16_ECC can correct 16 bit-flips per 512Bytes of data.
(b) BCH16_ECC generates 26-bytes of ECC syndrome / 512B.
Due to (b) this scheme can only be used with NAND devices which have enough
OOB to satisfy following equation:
OOBsize per page >= 26 * (page-size / 512)

Signed-off-by: Pekon Gupta

mtd: nand: omap_gpmc: use macro for register definitions

2014-06-06T21:46:08+00:00

GPMC can support simultaneous processing of 8 512Byte data chunks, in parallel

Signed-off-by: Pekon Gupta

mtd: nand: fix GET/SET_FEATURES address on 16-bit devices

2014-06-06T21:46:05+00:00

As per following Sections in ONFI Spec, GET_FEATURES and SET_FEATURES also need
byte-addressing on 16-bit devices.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

So porting following commit from linux kernel
    commit e34fcb07a6d57411de6e15a47724fbe92c5caa42
    Author: David Mosberger   (preserving authorship)
    mtd: nand: fix GET/SET_FEATURES address on 16-bit devices

Signed-off-by: Pekon Gupta

mtd: nand: force NAND_CMD_READID onto 8-bit bus

2014-06-06T21:46:03+00:00

As per following Sections in ONFI Spec, NAND_CMD_READID should use only
lower 8-bit for transfering command, address and data even on x16 NAND device.

*Section: Target Initialization"
"The Read ID and Read Parameter Page commands only use the lower 8-bits of the
 data bus. The host shall not issue commands that use a word data width on x16
 devices until the host determines the device supports a 16-bit data bus width
 in the parameter page."

*Section: Bus Width Requirements*
"When the host supports a 16-bit bus width, only data is transferred at the
 16-bit width. All address and command line transfers shall use only the lower
 8-bits of the data bus. During command transfers, the host may place any value
 on the upper 8-bits of the data bus. During address transfers, the host shall
 set the upper 8-bits of the data bus to 00h."

Thus porting  following commit from linux-kernel to ensure that column address
is not altered to align to x16 bus when issuing NAND_CMD_READID command.

    commit 3dad2344e92c6e1aeae42df1c4824f307c51bcc7
    mtd: nand: force NAND_CMD_READID onto 8-bit bus
    Author: Brian Norris  (preserving authorship)

    The NAND command helpers tend to automatically shift the column address
    for x16 bus devices, since most commands expect a word address, not a
    byte address. The Read ID command, however, expects an 8-bit address
    (i.e., 0x00, 0x20, or 0x40 should not be translated to 0x00, 0x10, or
    0x20).

    This fixes the column address for a few drivers which imitate the
    nand_base defaults.

Signed-off-by: Pekon Gupta

mtd: nand: omap_elm: use macros for register definitions

2014-06-06T21:45:50+00:00

This patch adds macros for following parameters of ELM Hardware engine
 - ELM_MAX_CHANNELS: ELM can process 8 data streams simultaneously
 - ELM_MAX_ERRORS: ELM can detect upto 16 ECC error when using BCH16 scheme

Signed-off-by: Pekon Gupta 
Reviewed-by: Stefan Roese

mtd: nand: omap_elm: use bch_type instead of nibble count to differentiate between BCH4/BCH8/BCH16

2014-06-06T21:45:48+00:00

ELM hardware engine support ECC error detection for multiple ECC strengths like
 +------+------------------------+
 |Type  | ECC syndrome length    |
 +------+------------------------+
 |BCH4  | 6.5 bytes = 13 nibbles |
 |BCH8  | 13 byte = 26 nibbles   |
 |BCH16 | 26 bytes = 52 nibbles  |
 +------+------------------------+

Current implementation of omap_elm driver uses ECC syndrom length (in 'nibbles')
to differentiate between BCH4/BCH8/BCH16. This patch replaces it with 'bch_type'

Signed-off-by: Pekon Gupta 
Reviewed-by: Stefan Roese

mtd: delete unused files

2014-04-17T18:38:30+00:00

Signed-off-by: Masahiro Yamada 
Cc: Scott Wood