u-boot.git/include/mpc83xx.h, branch v1.3.2 Unnamed repository; edit this file 'description' to name the repository. mpc83xx: Fix the fatal conflict of merge 2008-01-17T17:01:52+00:00 Dave Liu r63238@freescale.com 2008-01-17T10:23:19+00:00 a8cb43a89be6cfd283257a603dd9841503ccce0f The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 will cause the mpc8315erdb board can't boot up. The patch fix that bug, and remove the duplicated #ifdef CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for MPC8313E processor. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> 
The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7
will cause the mpc8315erdb board can't boot up.

The patch fix that bug, and remove the duplicated #ifdef
CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for
MPC8313E processor.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
mpc83xx: add support for more system clock performance controls 2008-01-16T18:32:39+00:00 Kim Phillips kim.phillips@freescale.com 2008-01-16T18:06:16+00:00 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7 System registers that are modified are the Arbiter Configuration Register (ACR), the System Priority Control Register (SPCR), and the System Clock Configuration Register (SCCR). Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com> Signed-off by: Joe D'Abbraccio <ljd015@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> 
System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).

Signed-off by: Michael F. Reiss <Michael.F.Reiss@freescale.com>
Signed-off by: Joe D'Abbraccio <ljd015@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
mpc83xx: Fix the wrong definition of MPC8315E 2008-01-11T03:22:41+00:00 Dave Liu r63238@freescale.com 2008-01-10T15:06:05+00:00 6f3931a2bed5412c20d5e5536c865fbd657f7d28 According to the latest user manual of MPC8315E, 1) The SVCOD of HRCWL is different than 837x 2) The SCCR has changes Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> 
According to the latest user manual of MPC8315E,
1) The SVCOD of HRCWL is different than 837x
2) The SCCR has changes

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
mpc83xx: Fix the typo in mpc83xx.h 2008-01-11T03:20:30+00:00 Dave Liu r63238@freescale.com 2008-01-10T15:05:00+00:00 ec2638ea08a537a1bd409db873aaaa33a053ebae The SPCR about TSEC priority is wrong. Signed-off-by: Michael Barkowski <Michael.Barkowski@freescale.com> Signed-off-by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> 
The SPCR about TSEC priority is wrong.

Signed-off-by: Michael Barkowski <Michael.Barkowski@freescale.com>
Signed-off-by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
mpc83xx: Add the support of MPC8315E SoC 2008-01-08T15:55:39+00:00 Dave Liu r63238@freescale.com 2007-09-18T04:36:58+00:00 555da61702771fe0f76f3de23b4e7590f3704161 The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com> 
The MPC8315E SoC including e300c3 core and new IP blocks,
such as TDM, PCI Express and SATA controller.

Signed-off-by: Dave Liu <daveliu@freescale.com>
mpc83xx: Add the support of MPC837x SoC 2008-01-08T15:55:39+00:00 Dave Liu r63238@freescale.com 2007-09-18T04:36:11+00:00 03051c3d35c9981ceaa059005660e699f3eacf1c The MPC837x SoC including e300c4 core and new IP blocks, such as SDHC, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com> 
The MPC837x SoC including e300c4 core and new IP blocks,
such as SDHC, PCI Express and SATA controller.

Signed-off-by: Dave Liu <daveliu@freescale.com>
mpc83xx: implement board_add_ram_info 2007-08-17T04:12:24+00:00 Kim Phillips kim.phillips@freescale.com 2007-08-17T03:52:48+00:00 bbea46f76f767b919070b4829bf34c86bd223248 add board_add_ram_info, to make memory diagnostic output more consistent. u-boot banner output now looks like: DRAM: 256 MB (DDR1, 64-bit, ECC on) and for boards with SDRAM on the local bus, a line such as this is added: SDRAM: 64 MB (local bus) also replaced some magic numbers with their equivalent define names. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> 
add board_add_ram_info, to make memory diagnostic output more
consistent. u-boot banner output now looks like:

DRAM:  256 MB (DDR1, 64-bit, ECC on)

and for boards with SDRAM on the local bus, a line such as this is
added:

SDRAM: 64 MB (local bus)

also replaced some magic numbers with their equivalent define names.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Update SCCR programming in cpu_init_f() to support all 83xx processors 2007-08-10T06:12:03+00:00 Timur Tabi timur@freescale.com 2007-07-03T18:04:34+00:00 df33f6b4d6d63693dd9200808b242de1b86cb8e8 Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the bitfields for all 83xx processors. The code to update some bitfields was compiled only on some processors. Now, the bitfields are programmed as long as the corresponding CFG_SCCR option is defined in the board header file. This means that the board header file should not define any CFG_SCCR macros for bitfields that don't exist on that processor, otherwise the SCCR will be programmed incorrectly. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> 
Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the
bitfields for all 83xx processors.  The code to update some bitfields was
compiled only on some processors.  Now, the bitfields are programmed as long
as the corresponding CFG_SCCR option is defined in the board header file.
This means that the board header file should not define any CFG_SCCR macros
for bitfields that don't exist on that processor, otherwise the SCCR will be
programmed incorrectly.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
mpc83xx: Add support for 8360 silicon revision 2.1 2007-08-10T06:12:02+00:00 Lee Nipper Lee.Nipper@freescale.com 2007-06-15T01:07:33+00:00 1ded0242e437259366792d52b7e9d1e1931d8fa5 This change adds 8360 silicon revision 2.1 support to u-boot. Signed-off-by: Lee Nipper <lee.nipper@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> 
This change adds 8360 silicon revision 2.1 support to u-boot.

Signed-off-by: Lee Nipper <lee.nipper@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Coding stylke cleanup; rebuild CHANGELOG 2007-06-22T21:59:00+00:00 Wolfgang Denk wd@denx.de 2007-06-22T21:59:00+00:00 1636d1c8529c006d106287cfbc20cd0a246fe1cb