u-boot.git/include/mpc83xx.h, branch v1.3.4

fdt: add crypto node handling for MPC8{3, 5}xxE processors

2008-07-14T22:01:29+00:00

Delete the crypto node if not on an E-processor.  If on 8360 or 834x family,
check rev and up-rev crypto node (to SEC rev. 2.4 property values)
if on an 'EA' processor, e.g. MPC8349EA.

Signed-off-by: Kim Phillips

83xx/85xx/86xx: factor out Freescale Localbus defines out of mpc83xx.h

2008-06-10T17:28:08+00:00

This patch moves Freescale Localbus defines out of mpc83xx.h, so we could
use it on MPC85xx and MPC86xx processors.

Signed-off-by: Anton Vorontsov 
Acked-by: Andy Fleming 
Signed-off-by: Kim Phillips

Add missing CSCONFIG_BANK_BIT_3 define to mpc83xx.h

2008-06-10T17:19:04+00:00

Signed-off-by: Tor Krill 
Signed-off-by: Kim Phillips

mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) code

2008-03-28T21:01:06+00:00

in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6,
85xx's "Update SVR numbers to expand support", simplify SPRIDR processing
and processor ID display.  Add REVID_{MAJ,MIN}OR macros to make
REVID dependent code simpler.  Also added PARTID_NO_E and IS_E_PROCESSOR
convenience macros.

Signed-off-by: Kim Phillips

mpc83xx: MPC8360E-RDK: rework ddr setup, enable ecc

2008-03-26T00:16:47+00:00

Current DDR setup easily causes memory corruption, this patch fixes it.

Also fix TIMING_CFG0_MRS_CYC definition.

Signed-off-by: Anton Vorontsov

mpc8323erdb: Improve the system performance

2008-03-26T00:16:44+00:00

The following changes are based on kernel UCC ethernet performance:

1.  Make the CSB bus pipeline depth as 4, and enable the repeat mode
2.  Optimize transactions between QE and CSB.  Added CFG_SPCR_OPT
    switch to enable this setting.

The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:

3.  CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4.  CS0_CONFIG[ODT_WR_CONFIG] set to 1.  Was a reserved setting
    previously.
5.  TIMING_CFG_1[WRREC] is changed from 3clks to 2clks  (based on
    Twr=15ns, and this was already the setting in DDR_MODE)
6.  TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
    Trp=15ns)
7.  TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
    Tras=40ns)
8.  TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
    Trcd=15ns)
9.  TIMING_CFG_1[REFREC] changed from 21 clks to 11clks.  (based on
    Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks.  (based
    on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
    on CL=3 and WL=2).

Signed-off-by: Michael Barkowski 
Acked-by: Kim Phillips

mpc83xx: Fix the fatal conflict of merge

2008-01-17T17:01:52+00:00

The commit 9e89647889cd4b5ada5b5e7cad6cbe55737a08d7
will cause the mpc8315erdb board can't boot up.

The patch fix that bug, and remove the duplicated #ifdef
CFG_SPCR_TSECEP code and clean the SCCR_TSEC2 for
MPC8313E processor.

Signed-off-by: Dave Liu 
Signed-off-by: Kim Phillips

mpc83xx: add support for more system clock performance controls

2008-01-16T18:32:39+00:00

System registers that are modified are the Arbiter Configuration
Register (ACR), the System Priority Control Register (SPCR), and the
System Clock Configuration Register (SCCR).

Signed-off by: Michael F. Reiss 
Signed-off by: Joe D'Abbraccio 
Signed-off-by: Kim Phillips

mpc83xx: Fix the wrong definition of MPC8315E

2008-01-11T03:22:41+00:00

According to the latest user manual of MPC8315E,
1) The SVCOD of HRCWL is different than 837x
2) The SCCR has changes

Signed-off-by: Dave Liu 
Signed-off-by: Kim Phillips

mpc83xx: Fix the typo in mpc83xx.h

2008-01-11T03:20:30+00:00

The SPCR about TSEC priority is wrong.

Signed-off-by: Michael Barkowski 
Signed-off-by: Joe D'Abbraccio 
Signed-off-by: Dave Liu 
Signed-off-by: Kim Phillips